CD74HCT299

更新时间： 2024-01-21 16:31:35

品牌	Logo	应用领域
德州仪器 - TI		移位寄存器
页数	文件大小	规格书
10页	57K
描述
High Speed CMOS Logic 8-Bit Universal Shift Register; Three-State

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技术参数
数据手册
替代型号

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CD74HCT299 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	SOP, SOP20,.4	Reach Compliance Code：	unknown
风险等级：	5.92	JESD-30 代码：	R-PDSO-G20
JESD-609代码：	e0	最大频率@ Nom-Sup：	20000000 Hz
位数：	8	功能数量：	1
端子数量：	20	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP20,.4
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
电源：	5 V	子类别：	Shift Registers
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
Base Number Matches：	1

CD74HCT299 数据手册

CD74HC299,

CD74HCT299

Data sheet acquired from Harris Semiconductor

SCHS178

High Speed CMOS Logic

8-Bit Universal Shift Register; Three-State

January 1998

Features

Description

• Buffered Inputs

The Harris CD74HC259 and CD74HCT299 are 8-bit

shift/storage registers with three-state bus interface

capability. The register has four synchronous-operating

modes controlled by the two select inputs as shown in the

mode select (S0, S1) table. The mode select, the serial data

• Four Operating Modes: Shift Left, Shift Right, Load

and Store

[ /Title

(CD74

HC299

CD74

HCT29

• Can be Cascaded for N-Bit Word Lengths

(DS0, DS7) and the parallel data (I/O - I/O ) respond only

• I/O - I/O Bus Drive Capability and Three-State for

Bus Oriented Applications

to the low-to-high transition of the clock (CP) pulse. S0, S1

and data inputs must be one set-up time prior to the clock

positive transition.

• Typical f = 50MHz at V

= 5V, C = 15pF, T = 25 C

MAX CC

The Master Reset (MR) is an asynchronous active low input.

When MR output is low, the register is cleared regardless of

the status of all other inputs. The register can be expanded

by cascading same units by tying the serial output (Q0) to

the serial data (DS7) input of the preceding register, and

tying the serial output (Q7) to the serial data (DS0) input of

the following register. Recirculating the (n x 8) bits is

accomplished by tying the Q7 of the last stage to the DS0 of

the ﬁrst stage.

• Fanout (Over Temperature Range)

/Sub-

ject

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

(High

Speed

CMOS

Logic

8-Bit

Uni-

• Wide Operating Temperature Range . . . -55 C to 125 C

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

The three-state input/output I(/O) port has three modes of

operation:

• HC Types

- 2V to 6V Operation

versal

Shift

- High Noise Immunity: N = 30%, N = 30% of V

IL IH CC

1. Both output enable (OE1 and OE2) inputs are low and S0

or S1 or both are low, the data in the register is presented

at the eight outputs.

at V

= 5V

• HCT Types

2. When both S0 and S1 are high, I/O terminals are in the

high impedance state but being input ports, ready for par-

allel data to be loaded into eight registers with one clock

transition regardless of the status of OE1 and OE2.

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V = 0.8V (Max), V = 2V (Min)

IL IH

- CMOS Input Compatibility, I ≤ 1µA at V , V

OL OH

3. Either one of the two output enable inputs being high will

force I/O terminals to be in the off-state. It is noted that

each I/O terminal is a three-state output and a CMOS

buffer input.

Pinout

CD74HC299, CD74HCT299

(PDIP, SOIC)

Ordering Information

TOP VIEW

PKG.

OE1

OE2

PART NUMBER TEMP. RANGE ( C) PACKAGE

NO.

E20.3

CD74HC299E

CD74HCT299E

CD74HC299M

CD74HCT299M

NOTES:

-55 to 125

20 Ld PDIP

18 DS7

17 Q7

I/O

20 Ld SOIC M20.3

16 I/O

I/O

14 I/O

13 I/O

1. When ordering, use the entire part number. Add the sufﬁx 96 to

obtain the variant in the tape and reel.

GND 10

11 DS0

2. Wafer and die for this part number is available which meets all

electrical specifications. Please contact your local sales office or

Harris customer service for ordering information.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

File Number 1485.1

12 3 4 5 6 7...10

中文翻译

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CD74HCT299 替代型号

型号	品牌	替代类型	描述	数据表
CD54HCT299	TI	功能相似	High-Speed CMOS Logic 8-Bit Universal Shift Register; Three-State

与CD74HCT299相关器件

型号	品牌	获取价格	描述	数据表
CD74HCT299E	TI	获取价格	High Speed CMOS Logic 8-Bit Universal Shift Register; Three-State
CD74HCT299EE4	TI	获取价格	High-Speed CMOS Logic 8-Bit Universal Shift Register; Three-State
CD74HCT299EN	ETC	获取价格	Logic IC
CD74HCT299EX	RENESAS	获取价格	IC,SHIFT REGISTER,HCT-CMOS,DIP,20PIN,PLASTIC
CD74HCT299F	ETC	获取价格	Logic IC
CD74HCT299H	RENESAS	获取价格	IC,SHIFT REGISTER,HCT-CMOS,DIE
CD74HCT299M	TI	获取价格	High Speed CMOS Logic 8-Bit Universal Shift Register; Three-State
CD74HCT299M96	TI	获取价格	High-Speed CMOS Logic 8-Bit Universal Shift Register; Three-State
CD74HCT299M96E4	TI	获取价格	High-Speed CMOS Logic 8-Bit Universal Shift Register; Three-State
CD74HCT299M96G4	TI	获取价格	High-Speed CMOS Logic 8-Bit Universal Shift Register; Three-State

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