5秒后页面跳转
CD74HCT299 PDF预览

CD74HCT299

更新时间: 2024-11-19 23:04:31
品牌 Logo 应用领域
德州仪器 - TI 移位寄存器
页数 文件大小 规格书
10页 57K
描述
High Speed CMOS Logic 8-Bit Universal Shift Register; Three-State

CD74HCT299 数据手册

 浏览型号CD74HCT299的Datasheet PDF文件第2页浏览型号CD74HCT299的Datasheet PDF文件第3页浏览型号CD74HCT299的Datasheet PDF文件第4页浏览型号CD74HCT299的Datasheet PDF文件第5页浏览型号CD74HCT299的Datasheet PDF文件第6页浏览型号CD74HCT299的Datasheet PDF文件第7页 
CD74HC299,  
CD74HCT299  
Data sheet acquired from Harris Semiconductor  
SCHS178  
High Speed CMOS Logic  
8-Bit Universal Shift Register; Three-State  
January 1998  
Features  
Description  
• Buffered Inputs  
The Harris CD74HC259 and CD74HCT299 are 8-bit  
shift/storage registers with three-state bus interface  
capability. The register has four synchronous-operating  
modes controlled by the two select inputs as shown in the  
mode select (S0, S1) table. The mode select, the serial data  
• Four Operating Modes: Shift Left, Shift Right, Load  
and Store  
[ /Title  
(CD74  
HC299  
,
CD74  
HCT29  
9)  
• Can be Cascaded for N-Bit Word Lengths  
(DS0, DS7) and the parallel data (I/O - I/O ) respond only  
0
7
• I/O - I/O Bus Drive Capability and Three-State for  
Bus Oriented Applications  
0
7
to the low-to-high transition of the clock (CP) pulse. S0, S1  
and data inputs must be one set-up time prior to the clock  
positive transition.  
o
• Typical f = 50MHz at V  
= 5V, C = 15pF, T = 25 C  
MAX CC  
L
A
The Master Reset (MR) is an asynchronous active low input.  
When MR output is low, the register is cleared regardless of  
the status of all other inputs. The register can be expanded  
by cascading same units by tying the serial output (Q0) to  
the serial data (DS7) input of the preceding register, and  
tying the serial output (Q7) to the serial data (DS0) input of  
the following register. Recirculating the (n x 8) bits is  
accomplished by tying the Q7 of the last stage to the DS0 of  
the first stage.  
• Fanout (Over Temperature Range)  
/Sub-  
ject  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
(High  
Speed  
CMOS  
Logic  
8-Bit  
Uni-  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
The three-state input/output I(/O) port has three modes of  
operation:  
• HC Types  
- 2V to 6V Operation  
versal  
Shift  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
1. Both output enable (OE1 and OE2) inputs are low and S0  
or S1 or both are low, the data in the register is presented  
at the eight outputs.  
at V  
= 5V  
CC  
• HCT Types  
2. When both S0 and S1 are high, I/O terminals are in the  
high impedance state but being input ports, ready for par-  
allel data to be loaded into eight registers with one clock  
transition regardless of the status of OE1 and OE2.  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I 1µA at V , V  
l
OL OH  
3. Either one of the two output enable inputs being high will  
force I/O terminals to be in the off-state. It is noted that  
each I/O terminal is a three-state output and a CMOS  
buffer input.  
Pinout  
CD74HC299, CD74HCT299  
(PDIP, SOIC)  
Ordering Information  
TOP VIEW  
PKG.  
1
2
3
4
5
6
7
8
9
V
S0  
OE1  
OE2  
20  
19  
o
PART NUMBER TEMP. RANGE ( C) PACKAGE  
CC  
NO.  
E20.3  
E20.3  
S1  
CD74HC299E  
CD74HCT299E  
CD74HC299M  
CD74HCT299M  
NOTES:  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
20 Ld PDIP  
20 Ld PDIP  
18 DS7  
17 Q7  
I/O  
6
I/O  
4
20 Ld SOIC M20.3  
20 Ld SOIC M20.3  
16 I/O  
7
I/O  
2
I/O  
15  
5
3
1
I/O  
0
14 I/O  
13 I/O  
12  
Q0  
1. When ordering, use the entire part number. Add the suffix 96 to  
obtain the variant in the tape and reel.  
MR  
CP  
GND 10  
11 DS0  
2. Wafer and die for this part number is available which meets all  
electrical specifications. Please contact your local sales office or  
Harris customer service for ordering information.  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
File Number 1485.1  
Copyright © Harris Corporation 1998  
1

CD74HCT299 替代型号

型号 品牌 替代类型 描述 数据表
CD54HCT299 TI

功能相似

High-Speed CMOS Logic 8-Bit Universal Shift Register; Three-State

与CD74HCT299相关器件

型号 品牌 获取价格 描述 数据表
CD74HCT299E TI

获取价格

High Speed CMOS Logic 8-Bit Universal Shift Register; Three-State
CD74HCT299EE4 TI

获取价格

High-Speed CMOS Logic 8-Bit Universal Shift Register; Three-State
CD74HCT299EN ETC

获取价格

Logic IC
CD74HCT299EX RENESAS

获取价格

IC,SHIFT REGISTER,HCT-CMOS,DIP,20PIN,PLASTIC
CD74HCT299F ETC

获取价格

Logic IC
CD74HCT299H RENESAS

获取价格

IC,SHIFT REGISTER,HCT-CMOS,DIE
CD74HCT299M TI

获取价格

High Speed CMOS Logic 8-Bit Universal Shift Register; Three-State
CD74HCT299M96 TI

获取价格

High-Speed CMOS Logic 8-Bit Universal Shift Register; Three-State
CD74HCT299M96E4 TI

获取价格

High-Speed CMOS Logic 8-Bit Universal Shift Register; Three-State
CD74HCT299M96G4 TI

获取价格

High-Speed CMOS Logic 8-Bit Universal Shift Register; Three-State