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CD74HC4094

更新时间: 2024-11-24 05:28:03
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哈里斯 - HARRIS 存储
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8页 69K
描述
High Speed CMOS Logic 8-Stage Shift and Store Bus Register, Three-State

CD74HC4094 数据手册

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CD74HC4094,  
CD74HCT4094  
Semiconductor  
High Speed CMOS Logic  
November 1997  
8-Stage Shift and Store Bus Register, Three-State  
Features  
Description  
• Buffered Inputs  
The Harris CD74HC4094 and CD74HCT4094 are 8-stage  
serial shift registers having a storage latch associated with  
• Separate Serial Outputs Synchronous to Both  
Positive and Negative Clock Edges For Cascading  
[ /Title  
(CD74H  
C4094,  
CD74H  
CT4094  
)
each stage for strobing data from the serial input to parallel  
buffered three-state outputs. The parallel outputs may be  
connected directly to common bus lines. Data is shifted on  
positive clock transitions. The data in each shift register  
stage is transferred to the storage register when the Strobe  
input is high. Data in the storage register appears at the  
outputs whenever the Output-Enable signal is high.  
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
/Sub-  
ject  
Two serial outputs are available for cascading a number of  
these devices. Data is available at the QS serial output  
1
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
terminal on positive clock edges to allow for high-speed  
operation in cascaded system in which the clock rise time is  
(High  
Speed  
CMOS  
Logic 8-  
fast. The same serial information, available at the QS  
terminal on the next negative clock edge, provides a means  
for cascading these devices when the clock rise time is slow.  
2
• HC Types  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5V  
CC  
Ordering Information  
• HCT Types  
PKG.  
- 4.5V to 5.5V Operation  
o
PART NUMBER TEMP. RANGE ( C) PACKAGE  
NO.  
E16.3  
E16.3  
- Direct LSTTL Input Logic Compatibility,  
CD74HC4094E  
CD74HCT4094E  
CD74HC4094M  
CD74HCT4094M  
NOTES:  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
16 Ld PDIP  
16 Ld PDIP  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I 1µA at V , V  
l
OL OH  
16 Ld SOIC M16.15  
16 Ld SOIC M16.15  
Pinout  
CD74HC4094, CD74HCT4094  
(PDIP, SOIC)  
1. When ordering, use the entire part number. Add the suffix 96 to  
obtain the variant in the tape and reel.  
TOP VIEW  
2. Wafer or die for this part number is available which meets all elec-  
trical specifications. Please contact your local sales office or  
Harris customer service for ordering information.  
STROBE  
DATA  
CP  
1
2
3
4
5
6
7
8
16 V  
CC  
15 OE  
14 Q  
13 Q  
12 Q  
11 Q  
4
5
6
7
Q
Q
Q
Q
0
1
2
3
10 QS  
2
9
QS  
GND  
1
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
File Number 1779.1  
Copyright © Harris Corporation 1997  
1

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