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CD74HC194MTG4 PDF预览

CD74HC194MTG4

更新时间: 2024-11-18 12:42:59
品牌 Logo 应用领域
德州仪器 - TI 移位寄存器
页数 文件大小 规格书
19页 554K
描述
High-Speed CMOS Logic 4-Bit Bidirectional Universal Shift Register

CD74HC194MTG4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP16,.25针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.07其他特性:HOLD MODE
计数方向:BIDIRECTIONAL系列:HC/UH
JESD-30 代码:R-PDSO-G16JESD-609代码:e4
长度:9.9 mm逻辑集成电路类型:PARALLEL IN PARALLEL OUT
最大频率@ Nom-Sup:20000000 Hz湿度敏感等级:1
位数:4功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
电源:2/6 V传播延迟(tpd):265 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Shift Registers最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:3.9 mm
最小 fmax:23 MHzBase Number Matches:1

CD74HC194MTG4 数据手册

 浏览型号CD74HC194MTG4的Datasheet PDF文件第2页浏览型号CD74HC194MTG4的Datasheet PDF文件第3页浏览型号CD74HC194MTG4的Datasheet PDF文件第4页浏览型号CD74HC194MTG4的Datasheet PDF文件第5页浏览型号CD74HC194MTG4的Datasheet PDF文件第6页浏览型号CD74HC194MTG4的Datasheet PDF文件第7页 
CD54HC194, CD74HC194,  
CD74HCT194  
Data sheet acquired from Harris Semiconductor  
SCHS164G  
High-Speed CMOS Logic  
4-Bit Bidirectional Universal Shift Register  
September 1997 - Revised May 2006  
Features  
Description  
• Four Operating Modes  
The ’HC194 and CD74HCT194 are 4-bit shift registers with  
Asynchronous Master Reset (MR). In the parallel mode (S0  
and S1 are high), data is loaded into the associated flip-flop  
and appears at the output after the positive transition of the  
clock input (CP). During parallel loading serial data flow is  
inhibited. Shift left and shift right are accomplished  
synchronously on the positive clock edge with serial data  
entered at the shift left (DSL) serial input for the shift left  
mode, and at the shift right (DSR) serial input for the shift  
- Shift Right, Shift Left, Hold and Reset  
• Synchronous Parallel or Serial Operation  
[ /Title  
(CD74  
HC194,  
CD74H  
CT194)  
/Sub-  
• Typical f  
MAX  
= 60MHz at V  
= 5V, C = 15pF,  
CC L  
o
T = 25 C  
A
• Asynchronous Master Reset  
• Fanout (Over Temperature Range)  
right mode. Clearing the register is accomplished by a Low  
applied to the Master Reset (MR) pin.  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
ject  
(High-  
Speed  
CMOS  
Logic  
4-Bit  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
Ordering Information  
TEMP. RANGE  
o
PART NUMBER  
CD54HC194F3A  
CD74HC194E  
( C)  
PACKAGE  
16 Ld CERDIP  
16 Ld PDIP  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
• HC Types  
- 2V to 6V Operation  
CD74HC194M  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOP  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5V  
CC  
CD74HC194MT  
CD74HC194M96  
CD74HC194NSR  
CD74HC194PW  
CD74HC194PWR  
CD74HC194PWT  
CD74HCT194E  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
16 Ld TSSOP  
16 Ld TSSOP  
16 Ld TSSOP  
16 Ld PDIP  
- CMOS Input Compatibility, I 1µA at V , V  
l
OL OH  
Pinout  
CD54HC194 (CERDIP)  
CD74HC194 (PDIP, SOIC, SOP, TSSOP)  
CD74HCT194 (PDIP)  
NOTE: When ordering, use the entire part number. The suffixes 96  
and R denote tape and reel. The suffix T denotes a small-quantity  
reel of 250.  
TOP VIEW  
MR  
1
2
3
4
5
6
7
8
16 V  
CC  
DSR  
15 Q  
14 Q  
13 Q  
12 Q  
0
1
2
3
D
D
D
D
0
1
2
3
11 CP  
10 S1  
DSL  
9
S0  
GND  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2006, Texas Instruments Incorporated  
1

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