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CD74HC194NSR96 PDF预览

CD74HC194NSR96

更新时间: 2024-11-01 23:41:19
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8页 37K
描述
SHIFT REGISTER|HC-CMOS|SOP|16PIN|PLASTIC

CD74HC194NSR96 数据手册

 浏览型号CD74HC194NSR96的Datasheet PDF文件第2页浏览型号CD74HC194NSR96的Datasheet PDF文件第3页浏览型号CD74HC194NSR96的Datasheet PDF文件第4页浏览型号CD74HC194NSR96的Datasheet PDF文件第5页浏览型号CD74HC194NSR96的Datasheet PDF文件第6页浏览型号CD74HC194NSR96的Datasheet PDF文件第7页 
CD54/74HC194,  
CD74HCT194  
Data sheet acquired from Harris Semiconductor  
SCHS164B  
High-Speed CMOS Logic  
4-Bit Bidirectional Universal Shift Register  
September 1997 - Revised March 2002  
Features  
Description  
• Four Operating Modes  
The ’HC194 and CD74HCT194 are 4-bit shift registers with  
Asynchronous Master Reset (MR). In the parallel mode (S0  
and S1 are high), data is loaded into the associated flip-flop  
and appears at the output after the positive transition of the  
clock input (CP). During parallel loading serial data flow is  
inhibited. Shift left and shift right are accomplished  
synchronously on the positive clock edge with serial data  
entered at the shift left (DSL) serial input for the shift right  
mode, and at the shift right (DSR) serial input for the shift left  
- Shift Right, Shift Left, Hold and Reset  
• Synchronous Parallel or Serial Operation  
[ /Title  
(CD74  
HC194,  
CD74H  
CT194)  
/Sub-  
• Typical f  
MAX  
= 60MHz at V  
= 5V, C = 15pF,  
CC L  
o
T = 25 C  
A
• Asynchronous Master Reset  
• Fanout (Over Temperature Range)  
mode. Clearing the register is accomplished by a Low  
applied to the Master Reset (MR) pin.  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
ject  
(High-  
Speed  
CMOS  
Logic  
4-Bit  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
Ordering Information  
TEMP. RANGE  
o
PART NUMBER  
CD54HC194F3A  
CD74HC194E  
CD74HC194M  
CD74HC194NSR  
CD74HCT194E  
NOTES:  
( C)  
PACKAGE  
16 Ld CERDIP  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOP  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
• HC Types  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5V  
CC  
• HCT Types  
16 Ld PDIP  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
1. When ordering, use the entire part number. Add the suffix 96 to  
obtain the variant in the tape and reel.  
IL  
IH  
- CMOS Input Compatibility, I 1µA at V , V  
OL OH  
l
2. Die for this part number is available which meets all electrical  
specifications. Please contact your local TI sales office or  
customer service for ordering information.  
Pinout  
CD54HC194  
(CERDIP)  
CD74HC194  
(PDIP, SOIC, SOP)  
CD74HCT194  
(PDIP, SOIC)  
TOP VIEW  
MR  
1
2
3
4
5
6
7
8
16 V  
CC  
DSR  
15 Q  
0
1
2
3
D
D
D
D
14 Q  
13 Q  
12 Q  
0
1
2
3
11 CP  
10 S1  
DSL  
9
S0  
GND  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2002, Texas Instruments Incorporated  
1

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