CD74HC195
Data sheet acquired from Harris Semiconductor
SCHS165
High Speed CMOS Logic
4-Bit Parallel Access Register
September 1997
Features
Description
• Asynchronous Master Reset
• J, K, (D) Inputs to First Stage
• Fully Synchronous Serial or Parallel Data Transfer
• Shift Right and Parallel Load Capability
• Complementary Output From Last Stage
• Buffered Inputs
The device is useful in a wide variety of shifting, counting
and storage applications. It performs serial, parallel, serial to
parallel, or parallel to serial data transfers at very high
speeds.
[ /Title
(CD74
HC195
)
/Sub-
ject
(High
Speed
CMOS
Logic
4-Bit
Paral-
lel
The two modes of operation, shift right (Q -Q ) and parallel
0
1
load, are controlled by the state of the Parallel Enable (PE)
input. Serial data enters the first flip-flop (Q ) via the J and K
0
inputs when the PE input is high, and is shifted one bit in the
direction Q -Q -Q -Q following each Low to High clock
0
1
2
3
• Typical f
MAX
= 50MHz at V = 5V,
CC
transition. The J and K inputs provide the flexibility of the JK-
type input for special applications and by tying the two pins
together, the simple D-type input for general applications.
The device appears as four common-clocked D flip-flops
when the PE input is Low. After the Low to High clock transi-
tion, data on the parallel inputs (D0-D3) is transferred to the
respective Q -Q outputs. Shift left operation (Q -Q ) can
o
C = 15pF, T = 25 C
L
A
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
0
3
3
2
be achieved by tying the Q outputs to the Dn-1 inputs and
n
holding the PE input low.
Access
Regis-
ter)
• Significant Power Reduction Compared to LSTTL
Logic ICs
All parallel and serial data transfers are synchronous, occurring
after each Low to High clock transition. The CD74HC195 series
utilizes edge triggering; therefore, there is no restriction on the
activity of the J, K, Pn and PE inputs for logic operations, other
than set-up and hold time requirements. A Low on the
asynchronous Master Reset (MR) input sets all Q outputs Low,
independent of any other input condition.
• HC Types
/Autho
- 2V to 6V Operation
- High Noise Immunity: N = 30%, N = 30%of V
at
IL
IH
CC
V
= 5V
CC
Ordering Information
PInout
PKG.
NO.
o
PART NUMBER TEMP. RANGE ( C) PACKAGE
CD74HC195
(PDIP, SOIC)
TOP VIEW
CD74HC195E
CD74HC195M
NOTES:
-55 to 125
-55 to 125
16 Ld PDIP
E16.3
16 Ld SOIC M16.15
MR
J
1
2
3
4
5
6
7
8
16 V
CC
15 Q
0
1
2
3
3
1. When ordering, use the entire part number.
K
14 Q
13 Q
12 Q
11 Q
2. Die for this part number is available which meets all electrical
specifications. Please contact your local sales office or Harris
customer service for ordering information.
D0
D1
D2
D3
GND
10 CP
PE
9
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 1482.1
Copyright © Harris Corporation 1997
1