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CD74HC194M96 PDF预览

CD74HC194M96

更新时间: 2024-11-18 05:18:15
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描述
High-Speed CMOS Logic 4-Bit Bidirectional Universal Shift Register

CD74HC194M96 数据手册

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CD54HC194, CD74HC194,  
CD74HCT194  
Data sheet acquired from Harris Semiconductor  
SCHS164G  
High-Speed CMOS Logic  
4-Bit Bidirectional Universal Shift Register  
September 1997 - Revised May 2006  
Features  
Description  
• Four Operating Modes  
The ’HC194 and CD74HCT194 are 4-bit shift registers with  
Asynchronous Master Reset (MR). In the parallel mode (S0  
and S1 are high), data is loaded into the associated flip-flop  
and appears at the output after the positive transition of the  
clock input (CP). During parallel loading serial data flow is  
inhibited. Shift left and shift right are accomplished  
synchronously on the positive clock edge with serial data  
entered at the shift left (DSL) serial input for the shift left  
mode, and at the shift right (DSR) serial input for the shift  
- Shift Right, Shift Left, Hold and Reset  
• Synchronous Parallel or Serial Operation  
[ /Title  
(CD74  
HC194,  
CD74H  
CT194)  
/Sub-  
• Typical f  
MAX  
= 60MHz at V  
= 5V, C = 15pF,  
CC L  
o
T = 25 C  
A
• Asynchronous Master Reset  
• Fanout (Over Temperature Range)  
right mode. Clearing the register is accomplished by a Low  
applied to the Master Reset (MR) pin.  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
ject  
(High-  
Speed  
CMOS  
Logic  
4-Bit  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
Ordering Information  
TEMP. RANGE  
o
PART NUMBER  
CD54HC194F3A  
CD74HC194E  
( C)  
PACKAGE  
16 Ld CERDIP  
16 Ld PDIP  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
• HC Types  
- 2V to 6V Operation  
CD74HC194M  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOP  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5V  
CC  
CD74HC194MT  
CD74HC194M96  
CD74HC194NSR  
CD74HC194PW  
CD74HC194PWR  
CD74HC194PWT  
CD74HCT194E  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
16 Ld TSSOP  
16 Ld TSSOP  
16 Ld TSSOP  
16 Ld PDIP  
- CMOS Input Compatibility, I 1µA at V , V  
l
OL OH  
Pinout  
CD54HC194 (CERDIP)  
CD74HC194 (PDIP, SOIC, SOP, TSSOP)  
CD74HCT194 (PDIP)  
NOTE: When ordering, use the entire part number. The suffixes 96  
and R denote tape and reel. The suffix T denotes a small-quantity  
reel of 250.  
TOP VIEW  
MR  
1
2
3
4
5
6
7
8
16 V  
CC  
DSR  
15 Q  
14 Q  
13 Q  
12 Q  
0
1
2
3
D
D
D
D
0
1
2
3
11 CP  
10 S1  
DSL  
9
S0  
GND  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2006, Texas Instruments Incorporated  
1

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