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CD74HC193M96G4 PDF预览

CD74HC193M96G4

更新时间： 2024-11-20 05:18:15
品牌 Logo 应用领域
德州仪器 - TI 计数器
页数 文件大小 规格书
20页 513K
描述
High-Speed CMOS Logic Presettable Synchronous 4-Bit Up/Down Counters

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CD74HC193M96G4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP, SOP16,.25针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.08其他特性：TCO UP AND TCO DOWN OUTPUTS; SEPARATE UP/DOWN CLOCK
计数方向：BIDIRECTIONAL系列：HC/UH
JESD-30 代码：R-PDSO-G16JESD-609代码：e4
长度：9.9 mm负载电容（CL）：50 pF
负载/预设输入：YES逻辑集成电路类型：BINARY COUNTER
最大频率@ Nom-Sup：17000000 Hz最大I（ol）：0.004 A
工作模式：SYNCHRONOUS湿度敏感等级：1
位数：4功能数量：1
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP16,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260电源：2/6 V
传播延迟（tpd）：325 ns认证状态：Not Qualified
座面最大高度：1.75 mm子类别：Counters
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：4.5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：3.9 mm最小 fmax：20 MHz
Base Number Matches：1

CD74HC193M96G4 数据手册

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CD54/74HC192,  
CD54/74HC193, CD54/74HCT193  
Data sheet acquired from Harris Semiconductor  
SCHS163F  
High-Speed CMOS Logic  
Presettable Synchronous 4-Bit Up/Down Counters  
September 1997 - Revised October 2003  
Presetting the counter to the number on the preset data inputs  
(P0-P3) is accomplished by a LOW asynchronous parallel  
Features  
• Synchronous Counting and Asynchronous  
Loading  
load input (PL). The counter is incremented on the low-to-high  
transition of the Clock-Up input (and a high level on the Clock-  
Down input) and decremented on the low to high transition of  
the Clock-Down input (and a high level on the Clock-up input).  
A high level on the MR input overrides any other input to clear  
the counter to its zero state. The Terminal Count up (carry)  
goes low half a clock period before the zero count is reached  
and returns to a high level at the zero count. The Terminal  
Count Down (borrow) in the count down mode likewise goes  
low half a clock period before the maximum count (9 in the  
192 and 15 in the 193) and returns to high at the maximum  
count. Cascading is effected by connecting the carry and  
borrow outputs of a less significant counter to the Clock-Up  
and Clock-Down inputs, respectively, of the next most  
significant counter.  
[ /Title  
(CD74  
HC192  
,
CD74  
HC193  
,
CD74  
HCT19  
3)  
• Two Outputs for N-Bit Cascading  
• Look-Ahead Carry for High-Speed Counting  
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
/Sub-  
ject  
• HC Types  
- 2V to 6V Operation  
If a decade counter is preset to an illegal state or assumes an  
illegal state when power is applied, it will return to the normal  
sequence in one count as shown in state diagram.  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
(High  
Speed  
CMOS  
Logic  
Preset-  
at V  
= 5V  
CC  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
Ordering Information  
TEMP. RANGE  
o
V = 0.8V (Max), V = 2V (Min)  
IL IH  
PART NUMBER  
CD54HC192F3A  
CD54HC193F3A  
CD54HCT193F3A  
CD74HC192E  
( C)  
PACKAGE  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld PDIP  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
OL OH  
l
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
Description  
The ’HC192, ’HC193 and ’HCT193 are asynchronously  
presettable BCD Decade and Binary Up/Down synchronous  
counters, respectively.  
CD74HC192NSR  
CD74HC192PW  
CD74HC192PWR  
CD74HC192PWT  
CD74HC193E  
16 Ld SOP  
16 Ld TSSOP  
16 Ld TSSOP  
16 Ld TSSOP  
16 Ld PDIP  
Pinout  
CD54HC192, CD54HC193, CD54HCT193 (CERDIP)  
CD74HC192 (PDIP, SOP, TSSOP)  
CD74HC193 (PDIP, SOIC)  
CD74HCT193 (PDIP)  
TOP VIEW  
CD74HC193M  
16 Ld SOIC  
P1  
Q1  
1
2
3
4
5
6
7
8
16 V  
CC  
CD74HC193MT  
CD74HC193M96  
CD74HCT193E  
16 Ld SOIC  
15 P0  
16 Ld SOIC  
Q0  
14 MR  
13 TCD  
12 TCU  
11 PL  
10 P2  
CPD  
CPU  
Q2  
16 Ld PDIP  
NOTE: When ordering, use the entire part number. The suffixes 96  
and R denote tape and reel. The suffix T denotes a small-quantity  
reel of 250.  
Q3  
9
P3  
GND  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1
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