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CD74HC192 PDF预览

CD74HC192

更新时间: 2024-11-01 23:04:27
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德州仪器 - TI 计数器
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11页 68K
描述
High Speed CMOS Logic Presettable Synchronous 4-Bit Up/Down Counters

CD74HC192 数据手册

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CD74HC192, CD74HC193,  
CD74HCT193  
Data sheet acquired from Harris Semiconductor  
SCHS163  
High Speed CMOS Logic  
Presettable Synchronous 4-Bit Up/Down Counters  
September 1997  
Features  
Description  
• Synchronous Counting and Asynchronous  
Loading  
The Harris CD74HC192, CD74HC193 and CD74HCT193 are  
asynchronously presettable BCD Decade and Binary  
Up/Down synchronous counters, respectively.  
[ /Title  
(CD74  
HC192  
,
CD74  
HC193  
,
CD74  
HCT19  
3)  
/Sub-  
ject  
(High  
Speed  
CMOS  
Logic  
Preset-  
• Two Outputs for N-Bit Cascading  
Presetting the counter to the number on the preset data inputs  
(P0-P3) is accomplished by a LOW asynchronous parallel  
load input (PL). The counter is incremented on the low-to-high  
transition of the Clock-Up input (and a high level on the Clock-  
Down input) and decremented on the low to high transition of  
the Clock-Down input (and a high level on the Clock-up input).  
A high level on the MR input overrides any other input to clear  
the counter to its zero state. The Terminal Count up (carry)  
goes low half a clock period before the zero count is reached  
and returns to a high level at the zero count. The Terminal  
Count Down (borrow) in the count down mode likewise goes  
low half a clock period before the maximum count (9 in the  
192 and 15 in the 193) and returns to high at the maximum  
count. Cascading is effected by connecting the carry and  
borrow outputs of a less significant counter to the Clock-Up  
and CLock-Down inputs, respectively, of the next most  
significant counter.  
• Look-Ahead Carry for High-Speed Counting  
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
• HC Types  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5V  
CC  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
If a decade counter is present to an illegal state or assumes  
an illegal state when power is applied, it will return to the  
normal sequence in one count as shown in state diagram.  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I 1µA at V , V  
l
OL OH  
Ordering Information  
Pinout  
TEMP. RANGE  
PKG.  
NO.  
o
PART NUMBER  
CD74HC192E  
CD74HC193E  
CD74HCT193E  
CD74HCT193M  
NOTES:  
( C)  
PACKAGE  
16 Ld PDIP  
16 Ld PDIP  
16 Ld PDIP  
16 Ld SOIC  
CD74HC192, CD74HC193, CD74HCT193  
(PDIP, SOIC)  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
E16.3  
TOP VIEW  
E16.3  
E16.3  
M16.15  
P1  
Q1  
1
2
3
4
5
6
7
8
16 V  
CC  
15 P0  
Q0  
14 MR  
13 TCD  
12 TCU  
11 PL  
10 P2  
CPD  
CPU  
Q2  
1. When ordering, use the entire part number. Add the suffix 96 to  
obtain the variant in the tape and reel.  
Q3  
2. Wafer or die for this part number is available which meets all elec-  
trical specifications. Please contact your local sales office or  
Harris customer service for ordering information.  
9
P3  
GND  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
File Number 1674.1  
Copyright © Harris Corporation 1997  
1

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