5秒后页面跳转
捷配首页

Datasheet > CD54HC192
CD54HC192 PDF预览

CD54HC192

更新时间： 2024-11-01 22:03:19
品牌 Logo 应用领域
德州仪器 - TI 计数器
页数 文件大小 规格书
16页 354K
描述
High-Speed CMOS Logic Presettable Synchronous 4-Bit Up/Down Counters

阅读下载

中文翻译

获取价格

CD54HC192 数据手册

 浏览型号CD54HC192的Datasheet PDF文件第2页浏览型号CD54HC192的Datasheet PDF文件第3页浏览型号CD54HC192的Datasheet PDF文件第4页浏览型号CD54HC192的Datasheet PDF文件第5页浏览型号CD54HC192的Datasheet PDF文件第6页浏览型号CD54HC192的Datasheet PDF文件第7页 
CD54/74HC192,  
CD54/74HC193, CD54/74HCT193  
Data sheet acquired from Harris Semiconductor  
SCHS163F  
High-Speed CMOS Logic  
Presettable Synchronous 4-Bit Up/Down Counters  
September 1997 - Revised October 2003  
Presetting the counter to the number on the preset data inputs  
(P0-P3) is accomplished by a LOW asynchronous parallel  
Features  
• Synchronous Counting and Asynchronous  
Loading  
load input (PL). The counter is incremented on the low-to-high  
transition of the Clock-Up input (and a high level on the Clock-  
Down input) and decremented on the low to high transition of  
the Clock-Down input (and a high level on the Clock-up input).  
A high level on the MR input overrides any other input to clear  
the counter to its zero state. The Terminal Count up (carry)  
goes low half a clock period before the zero count is reached  
and returns to a high level at the zero count. The Terminal  
Count Down (borrow) in the count down mode likewise goes  
low half a clock period before the maximum count (9 in the  
192 and 15 in the 193) and returns to high at the maximum  
count. Cascading is effected by connecting the carry and  
borrow outputs of a less significant counter to the Clock-Up  
and Clock-Down inputs, respectively, of the next most  
significant counter.  
[ /Title  
(CD74  
HC192  
,
CD74  
HC193  
,
CD74  
HCT19  
3)  
• Two Outputs for N-Bit Cascading  
• Look-Ahead Carry for High-Speed Counting  
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
/Sub-  
ject  
• HC Types  
- 2V to 6V Operation  
If a decade counter is preset to an illegal state or assumes an  
illegal state when power is applied, it will return to the normal  
sequence in one count as shown in state diagram.  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
(High  
Speed  
CMOS  
Logic  
Preset-  
at V  
= 5V  
CC  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
Ordering Information  
TEMP. RANGE  
o
V = 0.8V (Max), V = 2V (Min)  
IL IH  
PART NUMBER  
CD54HC192F3A  
CD54HC193F3A  
CD54HCT193F3A  
CD74HC192E  
( C)  
PACKAGE  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld PDIP  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
OL OH  
l
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
Description  
The ’HC192, ’HC193 and ’HCT193 are asynchronously  
presettable BCD Decade and Binary Up/Down synchronous  
counters, respectively.  
CD74HC192NSR  
CD74HC192PW  
CD74HC192PWR  
CD74HC192PWT  
CD74HC193E  
16 Ld SOP  
16 Ld TSSOP  
16 Ld TSSOP  
16 Ld TSSOP  
16 Ld PDIP  
Pinout  
CD54HC192, CD54HC193, CD54HCT193 (CERDIP)  
CD74HC192 (PDIP, SOP, TSSOP)  
CD74HC193 (PDIP, SOIC)  
CD74HCT193 (PDIP)  
TOP VIEW  
CD74HC193M  
16 Ld SOIC  
P1  
Q1  
1
2
3
4
5
6
7
8
16 V  
CC  
CD74HC193MT  
CD74HC193M96  
CD74HCT193E  
16 Ld SOIC  
15 P0  
16 Ld SOIC  
Q0  
14 MR  
13 TCD  
12 TCU  
11 PL  
10 P2  
CPD  
CPU  
Q2  
16 Ld PDIP  
NOTE: When ordering, use the entire part number. The suffixes 96  
and R denote tape and reel. The suffix T denotes a small-quantity  
reel of 250.  
Q3  
9
P3  
GND  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1
1234567...16

中文翻译

下载PDF

CD54HC192 替代型号

型号 品牌 替代类型 描述 数据表
CD74HC192 TI

功能相似

 High Speed CMOS Logic Presettable Synchronous 4-Bit Up/Down Counters

与CD54HC192相关器件

型号 品牌 获取价格 描述 数据表
CD54HC192_07 TI

获取价格

 		High-Speed CMOS Logic Presettable Synchronous 4-Bit Up/Down Counters
CD54HC192_08 TI

获取价格

 		High-Speed CMOS Logic Presettable Synchronous 4-Bit Up/Down Counters
CD54HC192_1 TI

获取价格

 		High-Speed CMOS Logic Presettable Synchronous 4-Bit Up/Down Counters
CD54HC192E ETC

获取价格

 		Logic IC
CD54HC192EN ETC

获取价格

 		Logic IC
CD54HC192F RENESAS

获取价格

 		CD54HC192F
CD54HC192F/3 RENESAS

获取价格

 		HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL DECADE COUNTER, CDIP16
CD54HC192F3A TI

获取价格

 		High-Speed CMOS Logic Presettable Synchronous 4-Bit Up/Down Counters
CD54HC192H/3 RENESAS

获取价格

 		Decade Counter, HC/UH Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional,
CD54HC192H/3A RENESAS

获取价格

 		HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL DECADE COUNTER, UUC16

与CD54HC192相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证