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CD74HC193E

更新时间： 2024-11-19 22:39:51
品牌 Logo 应用领域
德州仪器 - TI 计数器
页数 文件大小 规格书
11页 68K
描述
High Speed CMOS Logic Presettable Synchronous 4-Bit Up/Down Counters

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中文翻译

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CD74HC193E 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：DIP包装说明：DIP, DIP16,.3
针数：16Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：0.76Samacsys Confidence：3
Samacsys Status：ReleasedSamacsys PartID：181123
Samacsys Pin Count：16Samacsys Part Category：Integrated Circuit
Samacsys Package Category：Dual-In-Line PackagesSamacsys Footprint Name：N (R-PDIP-T16)
Samacsys Released Date：2015-06-25 00:00:00Is Samacsys：N
其他特性：TCO UP AND TCO DOWN OUTPUTS; SEPARATE UP/DOWN CLOCK计数方向：BIDIRECTIONAL
系列：HC/UHJESD-30 代码：R-PDIP-T16
JESD-609代码：e4长度：19.3 mm
负载电容（CL）：50 pF负载/预设输入：YES
逻辑集成电路类型：BINARY COUNTER最大频率@ Nom-Sup：17000000 Hz
最大I（ol）：0.0052 A工作模式：SYNCHRONOUS
位数：4功能数量：1
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP16,.3
封装形状：RECTANGULAR封装形式：IN-LINE
包装方法：TUBE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：2/6 V最大电源电流（ICC）：0.08 mA
Prop。Delay @ Nom-Sup：46 ns传播延迟（tpd）：325 ns
认证状态：Not Qualified座面最大高度：5.08 mm
子类别：Counters最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：4.5 V
表面贴装：NO技术：CMOS
温度等级：MILITARY端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：6.35 mm
最小 fmax：20 MHzBase Number Matches：1

CD74HC193E 数据手册

 浏览型号CD74HC193E的Datasheet PDF文件第2页浏览型号CD74HC193E的Datasheet PDF文件第3页浏览型号CD74HC193E的Datasheet PDF文件第4页浏览型号CD74HC193E的Datasheet PDF文件第5页浏览型号CD74HC193E的Datasheet PDF文件第6页浏览型号CD74HC193E的Datasheet PDF文件第7页 
CD74HC192, CD74HC193,  
CD74HCT193  
Data sheet acquired from Harris Semiconductor  
SCHS163  
High Speed CMOS Logic  
Presettable Synchronous 4-Bit Up/Down Counters  
September 1997  
Features  
Description  
• Synchronous Counting and Asynchronous  
Loading  
The Harris CD74HC192, CD74HC193 and CD74HCT193 are  
asynchronously presettable BCD Decade and Binary  
Up/Down synchronous counters, respectively.  
[ /Title  
(CD74  
HC192  
,
CD74  
HC193  
,
CD74  
HCT19  
3)  
/Sub-  
ject  
(High  
Speed  
CMOS  
Logic  
Preset-  
• Two Outputs for N-Bit Cascading  
Presetting the counter to the number on the preset data inputs  
(P0-P3) is accomplished by a LOW asynchronous parallel  
load input (PL). The counter is incremented on the low-to-high  
transition of the Clock-Up input (and a high level on the Clock-  
Down input) and decremented on the low to high transition of  
the Clock-Down input (and a high level on the Clock-up input).  
A high level on the MR input overrides any other input to clear  
the counter to its zero state. The Terminal Count up (carry)  
goes low half a clock period before the zero count is reached  
and returns to a high level at the zero count. The Terminal  
Count Down (borrow) in the count down mode likewise goes  
low half a clock period before the maximum count (9 in the  
192 and 15 in the 193) and returns to high at the maximum  
count. Cascading is effected by connecting the carry and  
borrow outputs of a less significant counter to the Clock-Up  
and CLock-Down inputs, respectively, of the next most  
significant counter.  
• Look-Ahead Carry for High-Speed Counting  
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
• HC Types  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5V  
CC  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
If a decade counter is present to an illegal state or assumes  
an illegal state when power is applied, it will return to the  
normal sequence in one count as shown in state diagram.  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
l
OL OH  
Ordering Information  
Pinout  
TEMP. RANGE  
PKG.  
NO.  
o
PART NUMBER  
CD74HC192E  
CD74HC193E  
CD74HCT193E  
CD74HCT193M  
NOTES:  
( C)  
PACKAGE  
16 Ld PDIP  
16 Ld PDIP  
16 Ld PDIP  
16 Ld SOIC  
CD74HC192, CD74HC193, CD74HCT193  
(PDIP, SOIC)  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
E16.3  
TOP VIEW  
E16.3  
E16.3  
M16.15  
P1  
Q1  
1
2
3
4
5
6
7
8
16 V  
CC  
15 P0  
Q0  
14 MR  
13 TCD  
12 TCU  
11 PL  
10 P2  
CPD  
CPU  
Q2  
1. When ordering, use the entire part number. Add the suffix 96 to  
obtain the variant in the tape and reel.  
Q3  
2. Wafer or die for this part number is available which meets all elec-  
trical specifications. Please contact your local sales office or  
Harris customer service for ordering information.  
9
P3  
GND  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
File Number 1674.1  
Copyright © Harris Corporation 1997  
1
1234567...11

中文翻译

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CD74HC193E 替代型号

型号 品牌 替代类型 描述 数据表
SNJ54HC193J TI

完全替代

 4-BIT SYNCHRONOUS UP/DOWN COUNTERS DUAL CLOCK WITH CLEAR
CD74HC193MT TI

完全替代

 High-Speed CMOS Logic Presettable Synchronous 4-Bit Up/Down Counters
CD74HC193M TI

完全替代

 High-Speed CMOS Logic Presettable Synchronous 4-Bit Up/Down Counters

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 		High-Speed CMOS Logic Presettable Synchronous 4-Bit Up/Down Counters
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CD74HC193M96E4 TI

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