CD74HC174,
CD74HCT174
Data sheet acquired from Harris Semiconductor
SCHS159
High Speed CMOS Logic
August 1997
Hex D-Type Flip-Flop with Reset
Features
Description
• Buffered Positive Edge Triggered Clock
• Asynchronous Common Reset
The Harris CD74HC174 and CD74HCT174 are edge
triggered flip-flops which utilize silicon gate CMOS circuitry to
implement D-type flip-flops. They possess low power and
speeds comparable to low power Schottky TTL circuits. The
devices contain six master-slave flip-flops with a common
clock and common reset. Data on the D input having the
specified setup and hold times is transferred to the Q output
on the low to high transition of the CLOCK input. The MR
input, when low, sets all outputs to a low state.
[ /Title
(CD74
HC174
,
CD74
HCT17
4)
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
Each output can drive ten low power Schottky TTL
equivalent loads. The CD74HCT174 is functional as well as,
pin compatible to the 74LS174.
/Sub-
ject
• HC Types
- 2V to 6V Operation
(High
Speed
CMOS
Logic
Hex D-
Type
Ordering Information
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
at V
= 5V
CC
TEMP. RANGE
PKG.
NO.
o
• HCT Types
- 4.5V to 5.5V Operation
PART NUMBER
CD74HC174E
CD74HCT174E
CD74HC174M
CD74HCT174M
CD74HCT174W
NOTES:
( C)
PACKAGE
16 Ld PDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
Wafer
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
E16.3
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL
IH
E16.3
- CMOS Input Compatibility, I ≤ 1µA at V , V
Flip-
Flop
l
OL OH
M16.15
M16.15
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Die for this part number is available which meets all electrical
specifications. Please contact your local sales office or Harris
customer service for ordering information.
Pinout
CD74HC174, CD74HCT174
(PDIP, SOIC)
TOP VIEW
MR
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
Q
Q
0
5
5
4
D
D
Q
D
Q
D
D
0
1
1
2
2
Q
4
D
3
Q
3
CP
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 1608.1
Copyright © Harris Corporation 1997
1