CD74HC173,
CD74HCT173
Data sheet acquired from Harris Semiconductor
SCHS158
High Speed CMOS Logic
February 1998
Quad D-Type Flip-Flop, Three-State
Features
Description
• Three-State Buffered Outputs
• Gated Input and Output Enables
The Harris CD74HC173 and CD74HCT173 high speed
three-state quad D-type flip-flops are fabricated with silicon
gate CMOS technology. They possess the low power con-
sumption of standard CMOS Integrated circuits, and can
operate at speeds comparable to the equivalent low power
Schottky devices. The buffered outputs can drive 15 LSTTL
loads. The large output drive capability and three-state fea-
ture make these parts ideally suited for interfacing with bus
lines in bus oriented systems.
[ /Title
(CD74H
C173,
CD74H
CT173)
/Subject
(High
Speed
CMOS
Logic
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
The four D-type flip-flops operate synchronously from a com-
mon clock. The outputs are in the three-state mode when
either of the two output disable pins are at the logic “1” level.
The input ENABLES allow the flip-flops to remain in their
present states without having to disrupt the clock If either of
the 2 input ENABLES are taken to a logic “1” level, the Q
outputs are fed back to the inputs, forcing the flip-flops to
remain in the same state. Reset is enabled by taking the
MASTER RESET (MR) input to a logic “1” level. The data
outputs change state on the positive going edge of the clock.
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N = 30%, N = 30% of V
CC
IL
IH
at V
= 5V
CC
Quad D-
Type
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
l
OL OH
The CD74HCT173 logic family is functionally, as well as pin
compatible with the standard 74LS logic family.
Pinout
Ordering Information
CD74HC173, CD74HC173
(PDIP, SOIC)
TEMP. RANGE
PKG.
NO.
o
TOP VIEW
PART NUMBER
CD74HC173E
CD74HCT173E
CD74HC173M
CD74HCT173M
NOTES:
( C)
PACKAGE
16 Ld PDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
-55 to 125
-55 to 125
-55 to 125
-55 to 125
E16.3
OE
1
2
3
4
5
6
7
8
16 V
CC
15 MR
14 D0
13 D1
12 D2
11 D3
10 E2
OE2
E16.3
Q
Q
Q
Q
0
1
2
3
M16.15
M16.15
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
CP
9
E1
GND
2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 1641.1
Copyright © Harris Corporation 1998
1