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CD74HC165M96E4 PDF预览

CD74HC165M96E4

更新时间: 2024-11-23 22:19:43
品牌 Logo 应用领域
德州仪器 - TI 移位寄存器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
13页 274K
描述
High-Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register

CD74HC165M96E4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:GREEN, PLASTIC, MS-012AC, SOIC-16针数:16
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.05
Is Samacsys:N其他特性:SISO OPERATION ALSO AVAILABLE
计数方向:RIGHT系列:HC/UH
JESD-30 代码:R-PDSO-G16JESD-609代码:e4
长度:9.9 mm逻辑集成电路类型:PARALLEL IN SERIAL OUT
最大频率@ Nom-Sup:20000000 Hz湿度敏感等级:1
位数:8功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
电源:2/6 V传播延迟(tpd):250 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Shift Register最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:3.9 mm
最小 fmax:24 MHzBase Number Matches:1

CD74HC165M96E4 数据手册

 浏览型号CD74HC165M96E4的Datasheet PDF文件第2页浏览型号CD74HC165M96E4的Datasheet PDF文件第3页浏览型号CD74HC165M96E4的Datasheet PDF文件第4页浏览型号CD74HC165M96E4的Datasheet PDF文件第5页浏览型号CD74HC165M96E4的Datasheet PDF文件第6页浏览型号CD74HC165M96E4的Datasheet PDF文件第7页 
CD54HC165, CD74HC165,  
CD54HCT165, CD74HCT165  
Data sheet acquired from Harris Semiconductor  
SCHS156C  
High-Speed CMOS Logic  
February 1998 - Revised October 2003  
8-Bit Parallel-In/Serial-Out Shift Register  
Features  
Description  
• Buffered Inputs  
The ’HC165 and ’HCT165 are 8-bit parallel or serial-in shift  
registers with complementary serial outputs (Q and Q )  
7
7
• Asynchronous Parallel Load  
• Complementary Outputs  
[ /Title  
(CD74H  
C165,  
CD74H  
CT165)  
/Subject  
(High  
available from the last stage. When the parallel load (PL)  
input is LOW, parallel data from the D0 to D7 inputs are  
loaded into the register asynchronously. When the PL is  
HIGH, data enters the register serially at the DS input and  
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
shifts one place to the right (Q Q Q , etc.) with each  
0
1
2
positive-going clock transition. This feature allows parallel-  
o
o
to-serial converter expansion by typing the Q output to the  
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
7
DS input of the succeeding device.  
For predictable operation the LOW-to-HIGH transition of CE  
should only take place while CP is HIGH. Also, CP an d CE  
should be LOW before the LOW-to-HIGH transition of PL to  
prevent shifting the data when PL goes HIGH.  
Speed  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
CMOS  
Logic 8-  
Bit Par-  
allel-  
• HC Types  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
CC  
Ordering Information  
IL  
IH  
at V  
= 5V  
CC  
TEMP. RANGE  
o
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
PART NUMBER  
CD54HC165F3A  
CD54HCT165F3A  
CD74HC165E  
( C)  
PACKAGE  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I 1µA at V , V  
l
OL OH  
CD74HC165M  
Pinout  
CD74HC165MT  
CD54HC165M96  
CD74HCT165E  
CD74HCT165M  
CD74HCT165MT  
CD54HCT165M96  
CD54HC165, CD54HCT165  
(CERDIP)  
CD74HC165, CD74HCT165  
(PDIP, SOIC)  
TOP VIEW  
PL  
CP  
D4  
D5  
D6  
D7  
1
2
3
4
5
6
7
8
16 V  
CC  
15 CE  
14 D3  
13 D2  
12 D1  
11 D0  
10 DS  
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel. The suffix T denotes a small-quantity reel of  
250.  
Q
7
9
Q
7
GND  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1

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