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CD74HC147NSR

更新时间： 2024-11-19 22:23:07
品牌 Logo 应用领域
德州仪器 - TI 逻辑集成电路光电二极管编码器
页数 文件大小 规格书
13页 347K
描述
High-Speed CMOS Logic 10- to 4-Line Priority Encoder

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CD74HC147NSR 数据手册

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CD54HC147, CD74HC147,  
CD74HCT147  
Data sheet acquired from Harris Semiconductor  
SCHS149F  
High-Speed CMOS Logic  
September 1997 - Revised November 2003  
10- to 4-Line Priority Encoder  
provide binary representation on the four active LOW inputs  
(Y0 to Y3). A priority is assigned to each input so that when  
two or more inputs are simultaneously active, the input with  
the highest priority is represented on the output, with input  
Features  
[ /Title  
(CD74  
HC147  
,
CD74  
HCT14  
7)  
• Buffered Inputs and Outputs  
• Typical Propagation Delay: 13ns at V  
o
= 5V,  
CC  
line l having the highest priority.  
9
C = 15pF, T = 25 C  
L
A
These devices provide the 10-line to 4-line priority encoding  
function by use of the implied decimal “zero”. The “zero” is  
encoded when all nine data inputs are HIGH, forcing all four  
outputs HIGH.  
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
/Sub-  
ject  
Ordering Information  
(High  
Speed  
CMOS  
Logic  
10-to-4  
Line  
Prior-  
ity  
Encode  
r)  
TEMP. RANGE  
o
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
PART NUMBER  
CD54HC147F3A  
CD74HC147E  
( C)  
PACKAGE  
16 Ld CERDIP  
16 Ld PDIP  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
• HC Types  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
CD74HC147M  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOP  
at V  
= 5V  
CC  
CD74HC147MT  
CD74HC147M96  
CD74HC147NSR  
CD74HC147PW  
CD74HC147PWR  
CD74HC147PWT  
CD74HCT147E  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
OL OH  
16 Ld TSSOP  
16 Ld TSSOP  
16 Ld TSSOP  
16 Ld PDIP  
l
/Autho  
r ()  
Description  
/Key-  
words  
(High  
Speed  
CMOS  
Logic  
10-to-4  
Line  
The ’HC147 and CD74HCT147 are high speed silicon-gate  
CMOS devices and are pin-compatible with low power  
Schottky TTL (LSTTL).  
NOTE: When ordering, use the entire part number. The suffixes  
96 and R denote tape and reel. The suffix T denotes a  
small-quantity reel of 250.  
The ’HC147 and CD74HCT147 9-input priority encoders  
accept data from nine active LOW inputs (l to l ) and  
1
9
Pinout  
Prior-  
ity  
CD54HC147 (CERDIP)  
CD74HC147 (PDIP, SOIC, SOP, TSSOP)  
CD74HCT147 (PDIP, TSSOP)  
TOP VIEW  
Encode  
r, High  
Speed  
CMOS  
Logic  
10-to-4  
Line  
I4  
I5  
1
2
3
4
5
6
7
8
16 V  
CC  
15 NC  
14 Y3  
13 I3  
12 I2  
11 I1  
10 I9  
I6  
I7  
I8  
Y2  
Y1  
GND  
Prior-  
ity  
9
Y0  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1
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CD74HC147NSR 替代型号

型号 品牌 替代类型 描述 数据表
CD74HC147NSRG4 TI

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