CD74HC147PWR

更新时间： 2024-02-25 06:06:26

品牌	Logo	应用领域
德州仪器 - TI		编码器
页数	文件大小	规格书
13页	347K
描述
High-Speed CMOS Logic 10- to 4-Line Priority Encoder

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数据手册
替代型号

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CD74HC147PWR 数据手册

CD54HC147, CD74HC147,

CD74HCT147

Data sheet acquired from Harris Semiconductor

SCHS149F

High-Speed CMOS Logic

September 1997 - Revised November 2003

10- to 4-Line Priority Encoder

provide binary representation on the four active LOW inputs

(Y0 to Y3). A priority is assigned to each input so that when

two or more inputs are simultaneously active, the input with

the highest priority is represented on the output, with input

Features

[ /Title

(CD74

HC147

CD74

HCT14

• Buffered Inputs and Outputs

• Typical Propagation Delay: 13ns at V

= 5V,

line l having the highest priority.

C = 15pF, T = 25 C

These devices provide the 10-line to 4-line priority encoding

function by use of the implied decimal “zero”. The “zero” is

encoded when all nine data inputs are HIGH, forcing all four

outputs HIGH.

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55 C to 125 C

• Balanced Propagation Delay and Transition Times

/Sub-

ject

Ordering Information

(High

Speed

CMOS

Logic

10-to-4

Line

Prior-

ity

Encode

TEMP. RANGE

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

PART NUMBER

CD54HC147F3A

CD74HC147E

( C)

PACKAGE

16 Ld CERDIP

16 Ld PDIP

-55 to 125

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N = 30%, N = 30% of V

IL IH CC

CD74HC147M

16 Ld SOIC

16 Ld SOP

at V

= 5V

CD74HC147MT

CD74HC147M96

CD74HC147NSR

CD74HC147PW

CD74HC147PWR

CD74HC147PWT

CD74HCT147E

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V = 0.8V (Max), V = 2V (Min)

IL IH

- CMOS Input Compatibility, I ≤ 1µA at V , V

OL OH

16 Ld TSSOP

16 Ld PDIP

/Autho

r ()

Description

/Key-

words

(High

Speed

CMOS

Logic

10-to-4

Line

The ’HC147 and CD74HCT147 are high speed silicon-gate

CMOS devices and are pin-compatible with low power

Schottky TTL (LSTTL).

NOTE: When ordering, use the entire part number. The sufﬁxes

96 and R denote tape and reel. The sufﬁx T denotes a

small-quantity reel of 250.

The ’HC147 and CD74HCT147 9-input priority encoders

accept data from nine active LOW inputs (l to l ) and

Pinout

Prior-

ity

CD54HC147 (CERDIP)

CD74HC147 (PDIP, SOIC, SOP, TSSOP)

CD74HCT147 (PDIP, TSSOP)

TOP VIEW

Encode

r, High

Speed

CMOS

Logic

10-to-4

Line

16 V

15 NC

14 Y3

13 I3

12 I2

11 I1

10 I9

GND

Prior-

ity

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

12 3 4 5 6 7...13

中文翻译

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CD74HC147PWR 替代型号

型号	品牌	替代类型	描述	数据表
CD74HC147PWE4	TI	完全替代	High-Speed CMOS Logic 10- to 4-Line Priority Encoder
CD74HC147PW	TI	完全替代	High-Speed CMOS Logic 10- to 4-Line Priority Encoder

与CD74HC147PWR相关器件

型号	品牌	获取价格	描述	数据表
CD74HC147PWRE4	TI	获取价格	High-Speed CMOS Logic 10- to 4-Line Priority Encoder
CD74HC147PWRG4	TI	获取价格	High-Speed CMOS Logic 10- to 4-Line Priority Encoder
CD74HC147PWT	TI	获取价格	High-Speed CMOS Logic 10- to 4-Line Priority Encoder
CD74HC147PWTE4	TI	获取价格	High-Speed CMOS Logic 10- to 4-Line Priority Encoder
CD74HC147PWTG4	TI	获取价格	High-Speed CMOS Logic 10- to 4-Line Priority Encoder
CD74HC14E	RENESAS	获取价格	HC/UH SERIES, HEX 1-INPUT INVERT GATE, PDIP14
CD74HC14E	TI	获取价格	High-Speed CMOS Logic Hex Inverting Schmitt Trigger
CD74HC14EE4	TI	获取价格	High-Speed CMOS Logic Hex Inverting Schmitt Trigger
CD74HC14EN	ETC	获取价格	Optoelectronic
CD74HC14EX	RENESAS	获取价格	HC/UH SERIES, HEX 1-INPUT INVERT GATE, PDIP14

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