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CD74HC147PWRG4 PDF预览

CD74HC147PWRG4

更新时间： 2024-11-02 05:18:11
品牌 Logo 应用领域
德州仪器 - TI 编码器
页数 文件大小 规格书
16页 401K
描述
High-Speed CMOS Logic 10- to 4-Line Priority Encoder

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CD74HC147PWRG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP, TSSOP16,.25针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.24其他特性：9 TO 4 LINE PRIORITY ENCODER
系列：HC/UHJESD-30 代码：R-PDSO-G16
JESD-609代码：e4长度：5 mm
逻辑集成电路类型：ENCODER湿度敏感等级：1
位数：9功能数量：1
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP16,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：2/6 V传播延迟（tpd）：240 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Arithmetic Circuits最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：4.5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：4.4 mmBase Number Matches：1

CD74HC147PWRG4 数据手册

 浏览型号CD74HC147PWRG4的Datasheet PDF文件第2页浏览型号CD74HC147PWRG4的Datasheet PDF文件第3页浏览型号CD74HC147PWRG4的Datasheet PDF文件第4页浏览型号CD74HC147PWRG4的Datasheet PDF文件第5页浏览型号CD74HC147PWRG4的Datasheet PDF文件第6页浏览型号CD74HC147PWRG4的Datasheet PDF文件第7页 
CD54HC147, CD74HC147,  
CD74HCT147  
Data sheet acquired from Harris Semiconductor  
SCHS149F  
High-Speed CMOS Logic  
September 1997 - Revised November 2003  
10- to 4-Line Priority Encoder  
provide binary representation on the four active LOW inputs  
(Y0 to Y3). A priority is assigned to each input so that when  
two or more inputs are simultaneously active, the input with  
the highest priority is represented on the output, with input  
Features  
[ /Title  
(CD74  
HC147  
,
CD74  
HCT14  
7)  
• Buffered Inputs and Outputs  
• Typical Propagation Delay: 13ns at V  
o
= 5V,  
CC  
line l having the highest priority.  
9
C = 15pF, T = 25 C  
L
A
These devices provide the 10-line to 4-line priority encoding  
function by use of the implied decimal “zero”. The “zero” is  
encoded when all nine data inputs are HIGH, forcing all four  
outputs HIGH.  
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
/Sub-  
ject  
Ordering Information  
(High  
Speed  
CMOS  
Logic  
10-to-4  
Line  
Prior-  
ity  
Encode  
r)  
TEMP. RANGE  
o
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
PART NUMBER  
CD54HC147F3A  
CD74HC147E  
( C)  
PACKAGE  
16 Ld CERDIP  
16 Ld PDIP  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
• HC Types  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
CD74HC147M  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOP  
at V  
= 5V  
CC  
CD74HC147MT  
CD74HC147M96  
CD74HC147NSR  
CD74HC147PW  
CD74HC147PWR  
CD74HC147PWT  
CD74HCT147E  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
OL OH  
16 Ld TSSOP  
16 Ld TSSOP  
16 Ld TSSOP  
16 Ld PDIP  
l
/Autho  
r ()  
Description  
/Key-  
words  
(High  
Speed  
CMOS  
Logic  
10-to-4  
Line  
The ’HC147 and CD74HCT147 are high speed silicon-gate  
CMOS devices and are pin-compatible with low power  
Schottky TTL (LSTTL).  
NOTE: When ordering, use the entire part number. The suffixes  
96 and R denote tape and reel. The suffix T denotes a  
small-quantity reel of 250.  
The ’HC147 and CD74HCT147 9-input priority encoders  
accept data from nine active LOW inputs (l to l ) and  
1
9
Pinout  
Prior-  
ity  
CD54HC147 (CERDIP)  
CD74HC147 (PDIP, SOIC, SOP, TSSOP)  
CD74HCT147 (PDIP, TSSOP)  
TOP VIEW  
Encode  
r, High  
Speed  
CMOS  
Logic  
10-to-4  
Line  
I4  
I5  
1
2
3
4
5
6
7
8
16 V  
CC  
15 NC  
14 Y3  
13 I3  
12 I2  
11 I1  
10 I9  
I6  
I7  
I8  
Y2  
Y1  
GND  
Prior-  
ity  
9
Y0  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1
1234567...16

中文翻译

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CD74HC147PWRG4 替代型号

型号 品牌 替代类型 描述 数据表
CD74HC147PWT TI

完全替代

 High-Speed CMOS Logic 10- to 4-Line Priority Encoder
CD74HC147PWR TI

完全替代

 High-Speed CMOS Logic 10- to 4-Line Priority Encoder
CD74HC147PW TI

完全替代

 High-Speed CMOS Logic 10- to 4-Line Priority Encoder

与CD74HC147PWRG4相关器件

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CD74HC147PWT TI

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 		High-Speed CMOS Logic 10- to 4-Line Priority Encoder
CD74HC147PWTE4 TI

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 		High-Speed CMOS Logic 10- to 4-Line Priority Encoder
CD74HC147PWTG4 TI

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 		High-Speed CMOS Logic 10- to 4-Line Priority Encoder
CD74HC14E RENESAS

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 		HC/UH SERIES, HEX 1-INPUT INVERT GATE, PDIP14
CD74HC14E TI

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 		High-Speed CMOS Logic Hex Inverting Schmitt Trigger
CD74HC14EE4 TI

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 		High-Speed CMOS Logic Hex Inverting Schmitt Trigger
CD74HC14EN ETC

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CD74HC14EX RENESAS

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 		HC/UH SERIES, HEX 1-INPUT INVERT GATE, PDIP14
CD74HC14H ETC

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CD74HC14M TI

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 		High-Speed CMOS Logic Hex Inverting Schmitt Trigger

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