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CD74HC138 PDF预览

CD74HC138

更新时间: 2024-10-31 23:04:27
品牌 Logo 应用领域
德州仪器 - TI 解码器解复用器
页数 文件大小 规格书
7页 45K
描述
High Speed CMOS Logic 3-to-8 Line Decoder/ Demultiplexer Inverting and Non-Inverting

CD74HC138 数据手册

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CD74HC138, CD74HCT138,  
CD74HC238, CD74HCT238  
Data sheet acquired from Harris Semiconductor  
SCHS147A  
High Speed CMOS Logic 3-to-8 Line Decoder/  
Demultiplexer Inverting and Non-Inverting  
October 1997 - Revised February 1999  
Features  
• Select One Of Eight Data Outputs  
Active Low for 138, Active High for 238  
[ /Title  
(CD74  
HC138  
,
CD74  
HCT13  
8,  
CD74  
HC238  
,
• l/O Port or Memory Selector  
• Three Enable Inputs to Simplify Cascading  
• Typical Propagation Delay of 13ns at V  
= 5V,  
CC  
o
C = 15pF, T = 25 C  
L
A
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
CD74  
HCT23  
8)  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
• HC Types  
/Sub-  
ject  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
(High  
Speed  
at V  
= 5V  
CC  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I 1µA at V , V  
OL OH  
l
Pinout  
CD74HC138, CD74HCT138, CD74HC238, CD74HCT238  
(PDIP, SOIC)  
TOP VIEW  
A0  
A1  
1
2
3
4
5
6
7
8
16 V  
CC  
15 Y0 (Y0)  
14 Y1 (Y1)  
13 Y2 (Y2)  
12 Y3 (Y3)  
11 Y4 (Y4)  
10 Y5 (Y5)  
A2  
E1  
E2  
E3  
(Y7) Y7  
GND  
9
Y6 (Y6)  
Signal names in parentheses are for ’HC238 and ’HCT238.  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 1999, Texas Instruments Incorporated  
1

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