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CD74ACT175M96G4 PDF预览

CD74ACT175M96G4

更新时间： 2024-09-16 14:48:47
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
13页 814K
描述
D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 4-Bit, Complementary Output, CMOS, PDSO16, GREEN, PLASTIC, MS-012AC, SOIC-16

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CD74ACT175M96G4 技术参数

生命周期：Contact Manufacturer包装说明：SOP,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.65Is Samacsys：N
系列：ACTJESD-30 代码：R-PDSO-G16
长度：9.9 mm逻辑集成电路类型：D FLIP-FLOP
位数：4功能数量：1
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C输出极性：COMPLEMENTARY
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
传播延迟（tpd）：11.5 ns座面最大高度：1.75 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL触发器类型：POSITIVE EDGE
宽度：3.9 mm最小 fmax：114 MHz
Base Number Matches：1

CD74ACT175M96G4 数据手册

 浏览型号CD74ACT175M96G4的Datasheet PDF文件第2页浏览型号CD74ACT175M96G4的Datasheet PDF文件第3页浏览型号CD74ACT175M96G4的Datasheet PDF文件第4页浏览型号CD74ACT175M96G4的Datasheet PDF文件第5页浏览型号CD74ACT175M96G4的Datasheet PDF文件第6页浏览型号CD74ACT175M96G4的Datasheet PDF文件第7页 
CD74ACT175  
QUADRUPLE D-TYPE FLIP-FLOP  
WITH CLEAR  
SCHS345 – APRIL 2003  
E OR M PACKAGE  
(TOP VIEW)  
Inputs Are TTL-Voltage Compatible  
Contains Four Flip-Flops With Double-Rail  
Outputs  
CLR  
1Q  
1
2
3
4
5
6
7
8
16  
V
CC  
Buffered Inputs  
15 4Q  
Speed of Bipolar F, AS, and S, With  
Significantly Reduced Power Consumption  
14  
13  
12  
11  
10  
9
1Q  
1D  
2D  
2Q  
2Q  
GND  
4Q  
4D  
3D  
3Q  
3Q  
CLK  
Balanced Propagation Delays  
±24-mA Output Drive Current  
– Fanout to 15 F Devices  
SCR-Latchup-Resistant CMOS Process and  
Circuit Design  
Exceeds 2-kV ESD Protection Per  
MIL-STD-883, Method 3015  
Applications Include:  
– Buffer/Storage Registers  
– Shift Registers  
– Pattern Generators  
description/ordering information  
This positive-edge-triggered D-type flip-flop has a direct clear (CLR) input. The CD74ACT175 features  
complementary outputs from each flip-flop.  
Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the  
positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not  
directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low  
level, the D input has no effect at the output.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP – E  
SOIC – M  
Tube  
Tube  
CD74ACT175E  
CD74ACT175M  
CD74ACT175E  
–55°C to 125°C  
ACT175M  
Tape and reel CD74ACT175M96  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUTS  
CLR  
L
CLK  
D
X
H
L
Q
L
Q
H
L
X
↑
H
H
L
H
↑
H
H
L
X
Q
Q
0
0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...13

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