Datasheet > CD54HC73_08

CD54HC73_08

更新时间： 2024-11-23 05:09:03

品牌	Logo	应用领域
德州仪器 - TI		触发器
页数	文件大小	规格书
15页	452K
描述
Dual J-K Flip-Flop with Reset Negative-Edge Trigger

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中文翻译

获取价格

数据手册

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CD54HC73_08 数据手册

CD54HC73, CD74HC73,

CD74HCT73

Data sheet acquired from Harris Semiconductor

SCHS134E

Dual J-K Flip-Flop with Reset

Negative-Edge Trigger

February 1998 - Revised September 2003

Features

Description

• Hysteresis on Clock Inputs for Improved Noise

Immunity and Increased Input Rise and Fall Times

The ’HC73 and CD74HCT73 utilize silicon gate CMOS

technology to achieve operating speeds equivalent to LSTTL

parts. They exhibit the low power consumption of standard

CMOS integrated circuits, together with the ability to drive 10

LSTTL loads.

[ /Title

(CD74

HC73,

CD74

HCT73

)

• Asynchronous Reset

• Complementary Outputs

• Buffered Inputs

These ﬂip-ﬂops have independent J, K, Reset and Clock

inputs and Q and Q outputs. They change state on the

negative-going transition of the clock pulse. Reset is

accomplished asynchronously by a low level input. This

device is functionally identical to the HC/HCT107 but differs

in terminal assignment and in some parametric limits.

• Typical f

MAX

= 60MHz at V = 5V, C = 15pF,

CC L

T = 25 C

/Sub-

ject

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

(Dual

J-K

Flip-

Flop

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads The HCT logic family is functionally as well as pin compatible

with the standard LS logic family.

• Wide Operating Temperature Range . . . -55 C to 125 C

• Balanced Propagation Delay and Transition Times

Ordering Information

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

TEMP. RANGE

PART NUMBER

CD54HC73F3A

CD74HC73E

( C)

PACKAGE

14 Ld CERDIP

14 Ld PDIP

14 Ld SOIC

14 Ld PDIP

14 Ld SOIC

-55 to 125

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N = 30%, N = 30% of V

IL IH CC

CD74HC73M

at V

= 5V

CD74HC73MT

CD74HC73M96

CD74HCT73E

CD74HCT73M

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V = 0.8V (Max), V = 2V (Min)

IL IH

- CMOS Input Compatibility, I ≤ 1µA at V , V

OL OH

NOTE: When ordering, use the entire part number. The sufﬁx 96

denotes tape and reel. The sufﬁx T denotes a small-quantity reel of

250.

Pinout

CD54HC73 (CERDIP)

CD74HC73, CD74HCT73 (PDIP, SOIC)

TOP VIEW

1CP

14 1J

13 1Q

12 1Q

11 GND

10 2K

2CP

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

12 3 4 5 6 7...15

中文翻译

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与CD54HC73_08相关器件

型号	品牌	获取价格	描述	数据表
CD54HC73_V01	TI	获取价格	Dual J-K Flip-Flop with Reset Negative-Edge Trigger
CD54HC73E	ETC	获取价格	Logic IC
CD54HC73EN	ETC	获取价格	Logic IC
CD54HC73F	RENESAS	获取价格	IC,FLIP-FLOP,DUAL,J/K TYPE,HC-CMOS,DIP,14PIN,CERAMIC
CD54HC73F	ROCHESTER	获取价格	HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14
CD54HC73F	TI	获取价格	Dual J-K Flip-Flop with Reset Negative-Edge Trigger
CD54HC73F/3	RENESAS	获取价格	HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14
CD54HC73F/3A	RENESAS	获取价格	IC HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14,
CD54HC73F3A	TI	获取价格	Dual J-K Flip-Flop with Reset Negative-Edge Trigger
CD54HC73F3A	RENESAS	获取价格	IC,FLIP-FLOP,DUAL,J/K TYPE,HC-CMOS,DIP,14PIN,CERAMIC

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