CD54HC4017, CD74HC4017
Data sheet acquired from Harris Semiconductor
SCHS200D
High-Speed CMOS Logic
Decade Counter/Divider with 10 Decoded Outputs
November 1997 - Revised October 2003
Features
Description
The ’HC4017 is a high speed silicon gate CMOS 5-stage
Johnson counter with 10 decoded outputs. Each of the
decoded outputs is normally low and sequentially goes high
on the low to high transition clock period of the 10 clock
period cycle. The CARRY (TC) output transitions low to high
after OUTPUT 10 goes from high to low, and can be used in
conjunction with the CLOCK ENABLE (CE) to cascade
several stages. The CLOCK ENABLE input disables
counting when in the high state. A RESET (MR) input is also
• Fully Static Operation
• Buffered Inputs
• Common Reset
• Positive Edge Clocking
[ /Title
(CD74
HC401
7)
/Sub-
ject
(High
Speed
CMOS
Logic
Decade
Counte
o
• Typical f
MAX
= 50MHz at V = 5V, C = 15pF, T = 25 C
CC L A
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads provided which when taken high sets all the decoded
outputs, except “0”, low.
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
o
o
The device can drive up to 10 low power Schottky equivalent
loads.
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
Ordering Information
• Significant Power Reduction Compared to LSTTL
Logic ICs
TEMP. RANGE
o
• HC Types
PART NUMBER
CD54HC4017F3A
CD74HC4017E
( C)
PACKAGE
16 Ld CERDIP
16 Ld PDIP
- 2V to 6V Operation
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
at V
= 5V
CC
CD74HC4017M
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld SOP
CD74HC4017MT
CD74HC4017M96
CD74HC4017NSR
CD74HC4017PW
CD74HC4017PWR
16 Ld TSSOP
16 Ld TSSOP
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
Pinout
CD54HC4017 (CERDIP)
CD74HC4017 (PDIP, SOIC, SOP, TSSOP)
TOP VIEW
5
1
2
3
4
5
6
7
8
16 V
CC
1
15 MR
14 CP
13 CE
12 TC
11 9
0
2
6
7
10 4
3
9
8
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1