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CD54HC174F3A PDF预览

CD54HC174F3A

更新时间: 2024-11-05 22:03:51
品牌 Logo 应用领域
德州仪器 - TI 触发器锁存器逻辑集成电路
页数 文件大小 规格书
12页 277K
描述
High-Speed CMOS Logic Hex D-Type Flip-Flop with Reset

CD54HC174F3A 技术参数

生命周期:Active零件包装代码:DIP
包装说明:DIP-16针数:16
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:6 weeks
风险等级:5.26Is Samacsys:N
其他特性:DUMMY VAL系列:HC/UH
JESD-30 代码:R-GDIP-T16长度:19.56 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:20000000 Hz最大I(ol):0.0052 A
位数:6功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:TRUE
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE包装方法:TUBE
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/6 V
最大电源电流(ICC):0.08 mAProp。Delay @ Nom-Sup:50 ns
传播延迟(tpd):250 ns认证状态:Not Qualified
筛选级别:38535Q/M;38534H;883B座面最大高度:5.08 mm
子类别:FF/Latches最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:6.92 mm最小 fmax:24 MHz
Base Number Matches:1

CD54HC174F3A 数据手册

 浏览型号CD54HC174F3A的Datasheet PDF文件第2页浏览型号CD54HC174F3A的Datasheet PDF文件第3页浏览型号CD54HC174F3A的Datasheet PDF文件第4页浏览型号CD54HC174F3A的Datasheet PDF文件第5页浏览型号CD54HC174F3A的Datasheet PDF文件第6页浏览型号CD54HC174F3A的Datasheet PDF文件第7页 
CD54HC174, CD74HC174,  
CD54HCT174, CD74HCT174  
Data sheet acquired from Harris Semiconductor  
SCHS159C  
High-Speed CMOS Logic  
Hex D-Type Flip-Flop with Reset  
August 1997 - Revised October 2003  
times is transferred to the Q output on the low to high  
transition of the CLOCK input. The MR input, when low, sets  
all outputs to a low state.  
Features  
• Buffered Positive Edge Triggered Clock  
• Asynchronous Common Reset  
[ /Title  
(CD74  
HC174  
,
CD74  
HCT17  
4)  
Each output can drive ten low power Schottky TTL  
equivalent loads. The ’HCT174 is functional as well as, pin  
compatible to the ’LS174.  
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
Ordering Information  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
TEMP. RANGE  
o
PART NUMBER  
CD54HC174F3A  
CD54HCT174F3A  
CD74HC174E  
( C)  
PACKAGE  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
/Sub-  
ject  
• HC Types  
- 2V to 6V Operation  
(High  
Speed  
CMOS  
Logic  
Hex D-  
Type  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5V  
CC  
CD74HC174M  
• HCT Types  
- 4.5V to 5.5V Operation  
CD74HC174MT  
CD74HC174M96  
CD74HCT174E  
CD74HCT174M  
CD74HCT174MT  
CD74HCT174M96  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL  
IH  
- CMOS Input Compatibility, I 1µA at V , V  
Flip-  
Flop  
l
OL OH  
Description  
The ’HC174 and ’HCT174 are edge triggered flip-flops which  
utilize silicon gate CMOS circuitry to implement D-type flip-  
flops. They possess low power and speeds comparable to low  
power Schottky TTL circuits. The devices contain six master-  
slave flip-flops with a common clock and common reset.  
Data on the D input having the specified setup and hold  
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel. The suffix T denotes a small-quantity reel of  
250.  
Pinout  
CD54HC174, CD54HCT174  
(CERDIP)  
CD74HC174, CD74HCT174  
(PDIP, SOIC)  
TOP VIEW  
MR  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
V
CC  
Q
Q
0
5
5
4
D
D
Q
D
Q
D
D
0
1
1
2
2
Q
4
D
3
Q
3
CP  
GND  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1

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