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CD54HC175_08 PDF预览

CD54HC175_08

更新时间: 2024-11-06 05:09:03
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德州仪器 - TI 触发器
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15页 562K
描述
High-Speed CMOS Logic Quad D-Type Flip-Flop with Reset

CD54HC175_08 数据手册

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CD54HC175, CD74HC175,  
CD54HCT175, CD74HCT175  
Data sheet acquired from Harris Semiconductor  
SCHS160C  
High-Speed CMOS Logic  
Quad D-Type Flip-Flop with Reset  
August 1997 - Revised October 2003  
advantage of standard CMOS ICs and the ability to drive 10  
LSTTL devices.  
Features  
• Common Clock and Asynchronous Reset on Four  
D-Type Flip-Flops  
Information at the D input is transferred to the Q, Q outputs on  
the positive going edge of the clock pulse. All four Flip-Flops  
are controlled by a common clock (CP) and a common reset  
(MR). Resetting is accomplished by a low voltage level  
independent of the clock. All four Q outputs are reset to a  
logic 0 and all four Q outputs to a logic 1.  
[ /Title  
(CD74  
HC175  
,
• Positive Edge Pulse Triggering  
• Complementary Outputs  
• Buffered Inputs  
CD74  
HCT17  
5)  
/Sub-  
ject  
(High  
Speed  
CMOS  
Logic  
Quad  
D-  
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
Ordering Information  
TEMP. RANGE  
o
o
o
PART NUMBER  
CD54HC175F3A  
CD54HCT175F3A  
CD74HC175E  
( C)  
PACKAGE  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
• HC Types  
- 2V to 6V Operation  
CD74HC175M  
- High Noise Immunity: N = 30%, N = 30% of V  
CC  
IL  
IH  
CD74HC175MT  
CD74HC175M96  
CD74HCT175E  
CD74HCT175M  
CD74HCT175MT  
CD74HCT175M96  
at V  
= 5V  
CC  
• HCT Types  
- 4.5V to 5.5V Operation  
Type  
Flip-  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL  
IH  
- CMOS Input Compatibility, I 1µA at V , V  
l
OL OH  
Description  
The ’HC175 and ’HCT175 are high speed Quad D-type Flip-  
Flops with individual D-inputs and Q, Q complementary  
outputs. The devices are fabricated using silicon gate CMOS  
technology. They have the low power consumption  
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel. The suffix T denotes a small-quantity reel of  
250.  
Pinout  
CD54HC175, CD54HCT175  
(CERDIP)  
CD74HC175, CD74HCT175  
(PDIP, SOIC)  
TOP VIEW  
MR  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
V
CC  
Q
Q
0
3
3
3
2
Q
D
D
Q
Q
Q
0
0
1
1
1
D
D
Q
Q
2
2
CP  
GND  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1

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