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CD4515BFMSR PDF预览

CD4515BFMSR

更新时间: 2024-11-03 19:53:59
品牌 Logo 应用领域
瑞萨 - RENESAS 驱动双倍数据速率输出元件逻辑集成电路
页数 文件大小 规格书
9页 93K
描述
4000/14000/40000 SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, CDIP24, FRIT SEALED, DIP-24

CD4515BFMSR 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP24,.6
针数:24Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.31系列:4000/14000/40000
输入调节:LATCHEDJESD-30 代码:R-GDIP-T24
JESD-609代码:e0负载电容(CL):50 pF
逻辑集成电路类型:OTHER DECODER/DRIVER最大I(ol):0.00036 A
功能数量:1端子数量:24
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:INVERTED封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP24,.6
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5/15 V
Prop。Delay @ Nom-Sup:1310 ns传播延迟(tpd):1310 ns
认证状态:Not Qualified筛选级别:MIL-PRF-38535 Class V
座面最大高度:5.72 mm子类别:Decoder/Drivers
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED总剂量:100k Rad(Si) V
宽度:15.24 mmBase Number Matches:1

CD4515BFMSR 数据手册

 浏览型号CD4515BFMSR的Datasheet PDF文件第2页浏览型号CD4515BFMSR的Datasheet PDF文件第3页浏览型号CD4515BFMSR的Datasheet PDF文件第4页浏览型号CD4515BFMSR的Datasheet PDF文件第5页浏览型号CD4515BFMSR的Datasheet PDF文件第6页浏览型号CD4515BFMSR的Datasheet PDF文件第7页 
CD4514BMS  
CD4515BMS  
CMOS 4-Bit  
Latch/4-to-16 Line Decoders  
December 1992  
Features  
Pinout  
CD4514BMS, CD4515BMS  
• High-Voltage Types (20-Volt Rating)  
• CD4514BMS Output “High” on Select  
• CD4515BMS Output “Low” on Select  
• Strobed Input Latch  
TOP VIEW  
1
2
3
4
5
6
7
8
9
24  
VDD  
STROBE  
DATA 1  
DATA 2  
S7  
23 INHIBIT  
22 DATA 4  
21 DATA 3  
20 S10  
• Inhibit Control  
• 100% Tested for Quiescent Current at 20V  
S6  
19 S11  
S5  
• Maximum Input Current of 1µA at 18V Over Full Pack-  
age Temperature Range; 100nA at 18V and 25oC  
18 S8  
S4  
17 S9  
S3  
S2  
• Noise Margin (Full Package-Temperature Range):  
- 1V at VDD = 5V  
16 S14  
S1 10  
S0 11  
15 S15  
- 2V at VDD = 10V  
14 S12  
- 2.5V at VDD = 15V  
VSS 12  
13 S13  
• 5V, 10V, and 15V Parametric Ratings  
• Standardized, Symmetrical Output Characteristics  
• Meets all Requirements of JEDEC Tentative Standard  
No. 13B, "Standard Specifications for Description of  
‘B’ Series CMOS Devices"  
Functional Diagram  
VDD = 24  
VSS = 12  
Applications  
11 S0  
S1  
10 S2  
• Digital Multiplexing  
• Address Decoding  
9
8
7
6
5
4
S3  
S4  
S5  
S6  
S7  
• Hexadecimal/BCD Decoding  
• Program-counter Decoding  
• Control Decoder  
DATA 1  
DATA 2  
2
3
A
B
C
D
4 TO 16  
DECODER  
LATCH  
DATA 3 21  
DATA 4 22  
18 S8  
17 S9  
20 S10  
19 S11  
14 S12  
13 S13  
16 S14  
15 S15  
Description  
STROBE  
1
CD4514BMS and CD4515BMS consist of a 4-bit strobed  
latch and a 4-to-16-line decoder. The latches hold the last  
input data presented prior to the strobe transition from 1 to 0.  
Inhibit control allows all outputs to be placed at  
0(CD4514BMS) or 1(CD4515BMS) regardless of the state of  
the data or strobe inputs.  
INHIBIT 23  
The decode truth table indicates all combinations of data  
inputs and appropriate selected outputs.  
These devices are similar to industry types MC14514 and  
MC14515.  
The CD4514BMS and CD4515BMS are supplied in these 24  
lead outline packages:  
Braze Seal DIP  
Frit Seal DIP  
H4V  
H1Z  
H4P  
Ceramic Flatpack  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 3195  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
7-1188  

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