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CD4516BCJ PDF预览

CD4516BCJ

更新时间： 2024-11-03 13:02:51
品牌 Logo 应用领域
美国国家半导体 - NSC 解码器驱动器锁存器
页数 文件大小 规格书
8页 147K
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中文翻译

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CD4516BCJ 数据手册

 浏览型号CD4516BCJ的Datasheet PDF文件第2页浏览型号CD4516BCJ的Datasheet PDF文件第3页浏览型号CD4516BCJ的Datasheet PDF文件第4页浏览型号CD4516BCJ的Datasheet PDF文件第5页浏览型号CD4516BCJ的Datasheet PDF文件第6页浏览型号CD4516BCJ的Datasheet PDF文件第7页 
February 1988  
CD4511BM/CD4511BC BCD-to-7 Segment  
Latch/Decoder/Driver  
General Description  
Features  
Y
Low logic circuit power dissipation  
The CD4511BM/CD4511BC BCD-to-seven segment latch/  
decoder/driver is constructed with complementary MOS  
(CMOS) enhancement mode devices and NPN bipolar out-  
put drivers in a single monolithic structure. The circuit pro-  
vides the functions of a 4-bit storage latch, an 8421 BCD-to-  
seven segment decoder, and an output drive capability.  
Lamp test (LT), blanking (BI), and latch enable (LE) inputs  
are used to test the display, to turn-off or pulse modulate  
the brightness of the display, and to store a BCD code,  
respectively. It can be used with seven-segment light emit-  
ting diodes (LED), incandescent, fluorescent, gas discharge,  
or liquid crystal readouts either directly or indirectly.  
Y
High current sourcing outputs (up to 25 mA)  
Latch storage of code  
Y
Y
Y
Y
Y
Y
Y
Blanking input  
Lamp test provision  
Readout blanking on all illegal input combinations  
Lamp intensity modulation capability  
Time share (multiplexing) facility  
Equivalent to Motorola MC14511  
Applications include instrument (e.g., counter, DVM, etc.)  
display driver, computer/calculator display driver, cockpit  
display driver, and various clock, watch, and timer uses.  
Connection Diagram  
Truth Table  
Inputs  
Outputs  
Dual-In-Line Package  
LE BI LT  
D
C
B
A
a
b
c
d
e
f
g
Display  
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
X
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
X
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
1
0
1
0
1
1
0
1
0
1
1
1
0
0
0
0
0
0
1
0
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
1
0
1
1
0
1
1
1
1
1
1
1
0
0
0
0
0
0
1
0
1
0
1
1
0
1
1
0
1
0
0
0
0
0
0
0
*
1
0
1
0
1
0
0
0
1
0
1
0
0
0
0
0
0
0
1
0
1
0
0
0
1
1
1
0
1
1
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
0
1
1
0
0
0
0
0
0
B
0
1
2
3
4
5
6
7
8
9
TL/F/5991–1  
Top View  
*
Order Number CD4511B  
e
X
Don’t Care  
*Depends upon the BCD code applied during the 0 to 1 transition of LE.  
Segment Identification  
Display  
TL/F/5991–3  
TL/F/5991–2  
C
1995 National Semiconductor Corporation  
TL/F/5991  
RRD-B30M105/Printed in U. S. A.  
12345678

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