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CD4515BC PDF预览

CD4515BC

更新时间: 2024-11-03 04:36:11
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 解码器
页数 文件大小 规格书
8页 236K
描述
4-Bit Latched/4-to-16 Line Decoders

CD4515BC 数据手册

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October 1987  
Revised January 2004  
CD4514BC CD4515BC  
4-Bit Latched/4-to-16 Line Decoders  
General Description  
Features  
The CD4514BC and CD4515BC are 4-to-16 line decoders  
with latched inputs implemented with complementary MOS  
(CMOS) circuits constructed with N- and P-channel  
enhancement mode transistors. These circuits are prima-  
rily used in decoding applications where low power dissipa-  
tion and/or high noise immunity is required.  
Wide supply voltage range: 3.0V to 15V  
High noise immunity: 0.45 VDD (typ.)  
Low power TTL: fan out of 2  
compatibility: driving 74L  
Low quiescent power dissipation:  
0.025 µW/package @ 5.0 VDC  
The CD4514BC (output active high option) presents a logi-  
cal “1” at the selected output, whereas the CD4515BC pre-  
sents a logical “0” at the selected output. The input latches  
are R–S type flip-flops, which hold the last input data pre-  
sented prior to the strobe transition from “1” to “0”. This  
input data is decoded and the corresponding output is acti-  
vated. An output inhibit line is also available.  
Single supply operation  
Input impedance = 1012typically  
Plug-in replacement for MC14514, MC14515  
Ordering Code:  
Order Number Package Number  
Package Diagram  
CD4514BCWM  
CD4514BCN  
M24B  
N24A  
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600" Wide  
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
CD4515BCWM  
(Note 1)  
M24B  
CD4515BCN  
N24A  
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600" Wide  
Note 1: Devices also available in Tape and Reel. Specify by appending suffix letter Xto the ordering code.  
Connection Diagram  
Top View  
© 2004 Fairchild Semiconductor Corporation  
DS005994  
www.fairchildsemi.com  

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