Datasheet > CD4502BFMSR

CD4502BFMSR

更新时间： 2024-11-05 07:02:55

品牌	Logo	应用领域
瑞萨 - RENESAS		驱动输出元件
页数	文件大小	规格书
8页	83K
描述
4000/14000/40000 SERIES, 6-BIT DRIVER, INVERTED OUTPUT, CDIP16, FRIT SEALED, CERAMIC, DIP-16

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数据手册

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CD4502BFMSR 数据手册

CD4502BMS

CMOS Strobed Hex Inverter/Buffer

December 1992

Features

Pinout

CD4502BMS

TOP VIEW

• High Voltage Type (20V Rating)

• 2 TTL Load Output Drive Capability

• 3 State Outputs

16 VDD

15 D6

• Common Output Disable Control

• Inhibit Control

14 Q6

3 STATE

OUTPUT DISABLE

• 100% Tested for Quiescent Current at 20V

• 5V, 10V and 15V Parametric Ratings

13 D5

12 INHIBIT

11 Q5

• Maximum Input Current of 1µA at 18V Over Full Pack-

age Temperature Range; 100nA at 18V and +25^oC

10 D4

• Noise Margin (Over Full Package/Temperature Range)

- 1V at VDD = 5V

VSS

9 Q4

- 2V at VDD = 10V

- 2.5V at VDD = 15V

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Speciﬁcations for Description of

‘B’ Series CMOS Devices”

Functional Diagram

Applications

• 3 State Hex Inverter for Interfacing ICs with Data

Buses

3 STATE

OUTPUT DISABLE

INHIBIT

• COS/MOS to TTL Hex Buffer

Description

CD4502BMS consists of six inverter/buffers with 3 state

outputs. A logic “1” on the OUTPUT DISABLE input

produces a high impedance state in all six outputs. This

feature permits common busing of the outputs, thus

simplifying system design. A Logic “1” on the INHIBIT input

switches all six outputs to logic “0” if the OUTPUT DISABLE

input is a logic “0”. This device is capable of driving two

standard TTL loads, which is equivalent to six times the

JEDEC “B” series IOL standard.

The CD4502BMS is supplied in these 16-lead outline packages:

VDD = 16

VSS = 8

Braze Seal DIP

Frit Seal DIP

H4T

H1F

H6W

Ceramic Flatpack

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 3334

7-473

12 3 4 5 6 7 8

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