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CD4502BMS PDF预览

CD4502BMS

更新时间: 2024-01-30 22:59:13
品牌 Logo 应用领域
英特矽尔 - INTERSIL /
页数 文件大小 规格书
8页 84K
描述
CMOS Strobed Hex Inverter/Buffer

CD4502BMS 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:GREEN, PLASTIC, TSSOP-16针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.48Is Samacsys:N
其他特性:WITH COMMON INHIBIT FOR ALL BITS控制类型:ENABLE LOW
系列:4000/14000/40000JESD-30 代码:R-PDSO-G16
JESD-609代码:e4长度:5 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
湿度敏感等级:1位数:6
功能数量:1端口数量:2
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:5/15 VProp。Delay @ Nom-Sup:380 ns
传播延迟(tpd):380 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):18 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4.4 mm
Base Number Matches:1

CD4502BMS 数据手册

 浏览型号CD4502BMS的Datasheet PDF文件第2页浏览型号CD4502BMS的Datasheet PDF文件第3页浏览型号CD4502BMS的Datasheet PDF文件第4页浏览型号CD4502BMS的Datasheet PDF文件第5页浏览型号CD4502BMS的Datasheet PDF文件第6页浏览型号CD4502BMS的Datasheet PDF文件第7页 
CD4502BMS  
CMOS Strobed Hex Inverter/Buffer  
December 1992  
Features  
Pinout  
CD4502BMS  
TOP VIEW  
• High Voltage Type (20V Rating)  
• 2 TTL Load Output Drive Capability  
• 3 State Outputs  
D3  
Q3  
D1  
1
2
3
4
5
6
7
8
16 VDD  
15 D6  
• Common Output Disable Control  
• Inhibit Control  
14 Q6  
3 STATE  
OUTPUT DISABLE  
• 100% Tested for Quiescent Current at 20V  
• 5V, 10V and 15V Parametric Ratings  
13 D5  
Q1  
12 INHIBIT  
11 Q5  
D2  
• Maximum Input Current of 1µA at 18V Over Full Pack-  
age Temperature Range; 100nA at 18V and +25oC  
10 D4  
Q2  
• Noise Margin (Over Full Package/Temperature Range)  
- 1V at VDD = 5V  
VSS  
9 Q4  
- 2V at VDD = 10V  
- 2.5V at VDD = 15V  
• Meets All Requirements of JEDEC Tentative Standard  
No. 13B, “Standard Specifications for Description of  
‘B’ Series CMOS Devices”  
Functional Diagram  
Applications  
• 3 State Hex Inverter for Interfacing ICs with Data  
Buses  
4
3 STATE  
OUTPUT DISABLE  
12  
3
INHIBIT  
D1  
5
7
• COS/MOS to TTL Hex Buffer  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
Description  
6
D2  
D3  
D4  
D5  
D6  
CD4502BMS consists of six inverter/buffers with 3 state  
outputs. A logic “1” on the OUTPUT DISABLE input  
produces a high impedance state in all six outputs. This  
feature permits common busing of the outputs, thus  
simplifying system design. A Logic “1” on the INHIBIT input  
switches all six outputs to logic “0” if the OUTPUT DISABLE  
input is a logic “0”. This device is capable of driving two  
standard TTL loads, which is equivalent to six times the  
JEDEC “B” series IOL standard.  
2
1
9
10  
13  
15  
11  
14  
The CD4502BMS is supplied in these 16-lead outline packages:  
VDD = 16  
VSS = 8  
Braze Seal DIP  
Frit Seal DIP  
H4T  
H1F  
H6W  
Ceramic Flatpack  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 3334  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
7-473  

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