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CD4503BCSJX PDF预览

CD4503BCSJX

更新时间: 2024-11-03 23:40:31
品牌 Logo 应用领域
其他 - ETC 驱动
页数 文件大小 规格书
7页 84K
描述
BUFFER/DRIVER|DUAL|2-BIT/4-BIT|CMOS|SOP|16PIN|PLASTIC

CD4503BCSJX 数据手册

 浏览型号CD4503BCSJX的Datasheet PDF文件第2页浏览型号CD4503BCSJX的Datasheet PDF文件第3页浏览型号CD4503BCSJX的Datasheet PDF文件第4页浏览型号CD4503BCSJX的Datasheet PDF文件第5页浏览型号CD4503BCSJX的Datasheet PDF文件第6页浏览型号CD4503BCSJX的Datasheet PDF文件第7页 
October 1987  
Revised April 2002  
CD4503BC  
Hex Non-Inverting 3-STATE Buffer  
General Description  
Features  
The CD4503BC is a hex non-inverting 3-STATE buffer with  
high output current sink and source capability. 3-STATE  
outputs make it useful in bus-oriented applications. Two  
separate disable inputs are provided. Buffers 1 through 4  
are controlled by the disable 4 input. Buffers 5 and 6 are  
controlled by the disable 2 input. A high level on either dis-  
able input will cause those gates on its control line to go  
into a high impedance state.  
Wide supply voltage range: 3.0 VDC to 18 VDC  
3-STATE outputs  
Symmetrical turn on/turn off delays  
Symmetrical output rise and fall times  
Pin-for-pin replacement for MM80C97 and MC14503  
Ordering Code:  
Order Number Package Number  
Package Description  
CD4503BCM  
CD4503BCSJ  
CD4503BCN  
M16A  
M16D  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Connection Diagram  
Schematic Diagram  
Truth Table  
In  
Disable  
Out  
Input  
0
0
0
1
0
1
1
X
3-STATE  
X = Don't Care  
Top View  
© 2002 Fairchild Semiconductor Corporation  
DS005989  
www.fairchildsemi.com  

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