Datasheet > CD4098BMS

CD4098BMS

更新时间： 2024-11-18 22:54:19

品牌	Logo	应用领域
英特矽尔 - INTERSIL		振荡器
页数	文件大小	规格书
11页	107K
描述
CMOS Dual Monostable Multivibrator

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CD4098BMS 数据手册

CD4098BMS

CMOS Dual Monostable Multivibrator

December 1992

Features

Description

• High Voltage Type (20V Rating)

CD4098BMS dual monostable multivibrator provides stable

retriggerable/resettable one shot operation for any ﬁxed volt-

age timing application.

• Retriggerable/Resettable Capability

• Trigger and Reset Propagation Delays Independent of

RX, CX

An external resistor (RX) and an external capacitor (CX)

control the timing for the circuit. Adjustment of RX and CX

provides a wide range of output pulse widths from the Q and

Q terminals. The time delay from trigger input to output

transition (trigger propagation delay) and the time delay from

reset input to output transition (reset propagation delay) are

independent of RX and CX.

• Triggering from Leading or Trailing Edge

• Q and Q Buffered Outputs Available

• Separate Resets

• Wide Range of Output Pulse Widths

• 100% Tested for Quiescent Current at 20V

• 5V, 10V and 15V Parametric Ratings

• Standardized Symmetrical Output Characteristics

Leading edge triggering (+TR) and trailing edge triggering

(-TR) inputs are provided for triggering from either edge of

an input pulse. An unused +TR input should be tied to VSS.

An unused -TR input should be tied to VDD. A RESET (on

low level) is provided for immediate termination of the output

pulse or to prevent output pulses when power is turned on.

An unused RESET input should be tied to VDD. However, if

an entire section of the CD4098BMS is not used, its RESET

should be tied to VSS. See Table 9.

• Maximum Input Current of 1µA at 18V Over Full Pack-

age Temperature Range; 100nA at 18V and +25^oC

• Noise Margin (Over Full Package/Temperature Range)

- 1V at VDD = 5V

- 2V at VDD = 10V

In normal operation the circuit triggers (extends the output

pulse one period) on the application of each new trigger

pulse. For operation in the non-retriggerable mode, Q is

connected to -TR when leading edge triggering (+TR) is

used or Q is connected to +TR when trailing edge triggering

(-TR) is used.

- 2.5V at VDD = 15V

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Speciﬁcations for Description of

‘B’ Series CMOS Devices”

Applications

The time period (T) for this multivibrator can be

approximated by: TX = ¹/₂RXCX for CX 3 0.01µF. Time

periods as a function of RX for values of CX and VDD are

given in Figure 8. Values of T vary from unit to unit and as a

function of voltage, temperature, and RXCX.

• Pulse Delay and Timing

• Pulse Shaping

Astable Multivibrator

The minimum value of external resistance, RX, is 5kΩ. The

maximum value of external capacitance, CX, is 100µF.

Figure 9 shows time periods as a function of CX for values of

RX and VDD.

Pinout

CD4098BMS

TOP VIEW

The output pulse width has variations of ±2.5% typically, over

the temperature range of -55^oC to +125^oC for CX = 1000pF

and RX = 100kΩ.

CX1

RXCX (1)

RESET (1)

+TR (1)

-TR (1)

16 VDD

For power supply variations of ±5%, the output pulse width

has variations of ±0.5% typically, for VDD = 10V and 15V

and ±1% typically, for VDD = 5V at CX = 1000pF and

RX = 5kΩ.

15 CX2

14 RXCX (2)

13 RESET (2)

12 +TR (2)

11 -TR (2)

10 Q2

The CD4098BMS is supplied in these 16-lead outline packages:

Braze Seal DIP

Frit Seal DIP

Ceramic Flatpack

H4T

H1F

H6W

VSS

TERMINALS 1, 8, 15 ARE ELECTRICALLY

CONNECTED INTERNALLY

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 3332

7-482

12 3 4 5 6 7...11

中文翻译

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与CD4098BMS相关器件

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CD4098BMT	TI	获取价格	CMOS DUAL MONASTABLE MULTIVIBRATOR
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CD4098BPWR	TI	获取价格	CMOS DUAL MONASTABLE MULTIVIBRATOR
CD4098BPWRE4	TI	获取价格	4000/14000/40000 SERIES, DUAL MONOSTABLE MULTIVIBRATOR, PDSO16, GREEN, PLASTIC, TSSOP-16
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CD4099B_12	TI	获取价格	CMOS 8-BIT ADDRESSABLE LATCH
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CD4099BCJ	NSC	获取价格	IC 4000/14000/40000 SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CDIP16, CERAMIC, DIP

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