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CD4099BC PDF预览

CD4099BC

更新时间: 2024-11-03 22:25:39
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 锁存器
页数 文件大小 规格书
6页 56K
描述
8-Bit Addressable Latch

CD4099BC 数据手册

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October 1987  
Revised January 1999  
CD4099BC  
8-Bit Addressable Latch  
address. Therefore, this should only be done while in the  
memory mode (E = HIGH, CL = LOW).  
General Description  
The CD4099BC is an 8-bit addressable latch with three  
address inputs (A0–A2), an active low enable input (E),  
active high clear input (CL), a data input (D), and eight out-  
puts (Q0–Q7).  
Features  
Wide supply voltage range: 3.0V to 15V  
High noise immunity: 0.45 VDD (typ.)  
Data is entered into a particular bit in the latch when that bit  
is addressed by the address inputs and the enable (E) is  
LOW. Data entry is inhibited when enable (E) is HIGH.  
Low power TTL: fan out of 2 driving 74L  
compatibility: or 1 driving 74LS  
Serial to parallel capability  
When clear (CL) and enable (E) are HIGH, all outputs are  
LOW. When clear (CL) is HIGH and enable (E) is LOW, the  
channel demultiplexing occurs. The bit that is addressed  
has an active output which follows the data input while all  
unaddressed bits are held LOW. When operating in the  
addressable latch mode (E = CL = LOW), changing more  
than one bit of the address could impose a transient wrong  
Storage register capability  
Random (addressable) data entry  
Active high demultiplexing capability  
Common active high clear  
Ordering Code:  
Order Number Package Number  
Package Description  
CD4099BCN  
N16E  
16-Lead Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Connection Diagram  
Pin Assignments for DIP  
Top View  
Truth Table  
Mode Selection  
E
CL  
Addressed  
Unaddressed  
Latch  
Mode  
Latch  
L
H
L
L
L
Follows Data  
Holds Previous Data Addressable Latch  
Holds Previous Data Holds Previous Data Memory  
H
H
Follows Data  
Reset to “0”  
Reset to “0”  
Reset to “0”  
Demultiplexer  
Clear  
H
© 1999 Fairchild Semiconductor Corporation  
DS005984.prf  
www.fairchildsemi.com  

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