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CD4076BFMSR PDF预览

CD4076BFMSR

更新时间: 2024-11-04 21:11:15
品牌 Logo 应用领域
瑞萨 - RENESAS 输出元件逻辑集成电路触发器
页数 文件大小 规格书
9页 77K
描述
4000/14000/40000 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDIP16, FRIT SEALED, CERAMIC, DIP-16

CD4076BFMSR 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP16,.3
针数:16Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.17
系列:4000/14000/40000JESD-30 代码:R-GDIP-T16
JESD-609代码:e0长度:6.5 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大I(ol):0.00036 A位数:4
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5/15 VProp。Delay @ Nom-Sup:810 ns
传播延迟(tpd):810 ns认证状态:Not Qualified
筛选级别:MIL-PRF-38535 Class V座面最大高度:5.08 mm
子类别:FF/Latches最大供电电压 (Vsup):18 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
总剂量:100k Rad(Si) V触发器类型:POSITIVE EDGE
宽度:7.62 mm最小 fmax:8 MHz
Base Number Matches:1

CD4076BFMSR 数据手册

 浏览型号CD4076BFMSR的Datasheet PDF文件第2页浏览型号CD4076BFMSR的Datasheet PDF文件第3页浏览型号CD4076BFMSR的Datasheet PDF文件第4页浏览型号CD4076BFMSR的Datasheet PDF文件第5页浏览型号CD4076BFMSR的Datasheet PDF文件第6页浏览型号CD4076BFMSR的Datasheet PDF文件第7页 
CD4076BMS  
CMOS 4 -Bit D-Type Registers  
December 1992  
Features  
Pinout  
CD4076BMS  
TOP VIEW  
• High Voltage Type (20V Rating)  
• Three State Outputs  
• Input Disabled Without Gating the Clock  
M
N
1
2
3
4
5
6
7
8
16 VDD  
OUTPUT  
DISABLE  
• Gated Output Control Lines for Enabling or Disabling  
the Outputs  
15 RESET  
14 DATA 1  
13 DATA 2  
12 DATA 3  
11 DATA 4  
Q1  
Q2  
Q3  
Q4  
• Standardized Symmetrical Output Characteristics  
• 100% Tested for Quiescent Current at 20V  
• Maximum Input Current of 1µA at 18V Over Full Pack-  
age Temperature Range; 100nA at 18V and +25oC  
DATA  
INPUT  
DISABLE  
10 G2  
G1  
CLOCK  
VSS  
• Noise Margin (Over Full Package/Temperature Range)  
- 1V at VDD = 5V  
9
- 2V at VDD = 10V  
- 2.5V at VDD = 15V  
• 5V, 10V and 15V Parametric Ratings  
Functional Diagram  
• Meets All Requirements of JEDEC Tentative Standard  
No. 13B, “Standard Specifications for Description of  
‘B’ Series CMOS Devices”  
DATA INPUT  
DISABLE  
OUTPUT  
DISABLE  
G1  
G2  
CLOCK  
7
M
N
Description  
9
10  
1
2
CD4076BMS types are four-bit registers consisting of D-type  
flip-flops that feature three-state outputs. Data Disable inputs  
are provided to control the entry of data into the flip-flops.  
When both Data Disable inputs are low, data at the D inputs  
are loaded into their respective flip-flops on the next positive  
transition of the clock input. Output Disable inputs are also  
provided. When the Output Disable inputs are both low, the  
normal logic states of the four outputs are available to the  
load. The outputs are disabled independently of the clock by  
a high logic level at either Output Disable input, and present  
a high impedance.  
14  
13  
3
4
D1  
D2  
D3  
D4  
Q1  
Q2  
Q3  
Q4  
4D - TYPE  
FLIP-FLOPS  
WITH  
AND-OR  
LOGIC  
12  
11  
5
6
15  
VSS = 8  
VDD = 16  
The CD4076BMS is supplied in these 16 lead outline pack-  
ages:  
RESET  
Braze Seal DIP  
Frit Seal DIP  
H4T  
H1E  
H6W  
Ceramic Flatpack  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 3325  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
7-1029  

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