5秒后页面跳转
CD4076BMS PDF预览

CD4076BMS

更新时间: 2024-10-25 22:54:19
品牌 Logo 应用领域
英特矽尔 - INTERSIL /
页数 文件大小 规格书
9页 81K
描述
CMOS 4 -Bit D-Type Registers

CD4076BMS 数据手册

 浏览型号CD4076BMS的Datasheet PDF文件第2页浏览型号CD4076BMS的Datasheet PDF文件第3页浏览型号CD4076BMS的Datasheet PDF文件第4页浏览型号CD4076BMS的Datasheet PDF文件第5页浏览型号CD4076BMS的Datasheet PDF文件第6页浏览型号CD4076BMS的Datasheet PDF文件第7页 
CD4076BMS  
CMOS 4 -Bit D-Type Registers  
December 1992  
Features  
Pinout  
CD4076BMS  
TOP VIEW  
• High Voltage Type (20V Rating)  
• Three State Outputs  
• Input Disabled Without Gating the Clock  
M
N
1
2
3
4
5
6
7
8
16 VDD  
OUTPUT  
DISABLE  
• Gated Output Control Lines for Enabling or Disabling  
the Outputs  
15 RESET  
14 DATA 1  
13 DATA 2  
12 DATA 3  
11 DATA 4  
Q1  
Q2  
Q3  
Q4  
• Standardized Symmetrical Output Characteristics  
• 100% Tested for Quiescent Current at 20V  
• Maximum Input Current of 1µA at 18V Over Full Pack-  
age Temperature Range; 100nA at 18V and +25oC  
DATA  
INPUT  
DISABLE  
10 G2  
G1  
CLOCK  
VSS  
• Noise Margin (Over Full Package/Temperature Range)  
- 1V at VDD = 5V  
9
- 2V at VDD = 10V  
- 2.5V at VDD = 15V  
• 5V, 10V and 15V Parametric Ratings  
Functional Diagram  
• Meets All Requirements of JEDEC Tentative Standard  
No. 13B, “Standard Specifications for Description of  
‘B’ Series CMOS Devices”  
DATA INPUT  
DISABLE  
OUTPUT  
DISABLE  
G1  
G2  
CLOCK  
7
M
N
Description  
9
10  
1
2
CD4076BMS types are four-bit registers consisting of D-type  
flip-flops that feature three-state outputs. Data Disable inputs  
are provided to control the entry of data into the flip-flops.  
When both Data Disable inputs are low, data at the D inputs  
are loaded into their respective flip-flops on the next positive  
transition of the clock input. Output Disable inputs are also  
provided. When the Output Disable inputs are both low, the  
normal logic states of the four outputs are available to the  
load. The outputs are disabled independently of the clock by  
a high logic level at either Output Disable input, and present  
a high impedance.  
14  
13  
3
4
D1  
D2  
D3  
D4  
Q1  
Q2  
Q3  
Q4  
4D - TYPE  
FLIP-FLOPS  
WITH  
AND-OR  
LOGIC  
12  
11  
5
6
15  
VSS = 8  
VDD = 16  
The CD4076BMS is supplied in these 16 lead outline pack-  
ages:  
RESET  
Braze Seal DIP  
Frit Seal DIP  
H4T  
H1E  
H6W  
Ceramic Flatpack  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 3325  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
7-1029  

与CD4076BMS相关器件

型号 品牌 获取价格 描述 数据表
CD4076BMT TI

获取价格

CMOS 4-BIT D-TYPE REGISTERS
CD4076BMTE4 TI

获取价格

4000/14000/40000 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16, GREEN,
CD4076BMW TI

获取价格

IC 4000/14000/40000 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDFP16, CERA
CD4076BMW/883 TI

获取价格

IC,FLIP-FLOP,QUAD,D TYPE,CMOS,FP,16PIN,CERAMIC
CD4076BMW/883B NSC

获取价格

IC,FLIP-FLOP,QUAD,D TYPE,CMOS,FP,16PIN,CERAMIC
CD4076BMW/883B TI

获取价格

IC,FLIP-FLOP,QUAD,D TYPE,CMOS,FP,16PIN,CERAMIC
CD4076BMW/883C NSC

获取价格

IC,FLIP-FLOP,QUAD,D TYPE,CMOS,FP,16PIN,CERAMIC
CD4076BMW/883C TI

获取价格

IC,FLIP-FLOP,QUAD,D TYPE,CMOS,FP,16PIN,CERAMIC
CD4076BMW-MIL NSC

获取价格

IC,FLIP-FLOP,QUAD,D TYPE,CMOS,FP,16PIN,CERAMIC
CD4076BMW-MIL TI

获取价格

IC,FLIP-FLOP,QUAD,D TYPE,CMOS,FP,16PIN,CERAMIC