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CD4077BCM PDF预览

CD4077BCM

更新时间: 2024-10-25 22:54:19
品牌 Logo 应用领域
美国国家半导体 - NSC 触发器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 124K
描述
Quad 2-Input EXCLUSIVE-OR, NOR Gate

CD4077BCM 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:SOP, SOP14,.25Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.13
系列:4000/14000/40000JESD-30 代码:R-PDSO-G14
JESD-609代码:e0长度:8.6235 mm
负载电容(CL):50 pF逻辑集成电路类型:XNOR GATE
功能数量:4输入次数:2
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5/15 V
Prop。Delay @ Nom-Sup:185 ns传播延迟(tpd):185 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:1.753 mm子类别:Gates
最大供电电压 (Vsup):15 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.9 mm
Base Number Matches:1

CD4077BCM 数据手册

 浏览型号CD4077BCM的Datasheet PDF文件第2页浏览型号CD4077BCM的Datasheet PDF文件第3页浏览型号CD4077BCM的Datasheet PDF文件第4页浏览型号CD4077BCM的Datasheet PDF文件第5页浏览型号CD4077BCM的Datasheet PDF文件第6页 
March 1992  
CD4070BM/CD4070BC  
Quad 2-Input EXCLUSIVE-OR Gate  
CD4077BM/CD4077BC  
Quad 2-Input EXCLUSIVE-NOR Gate  
General Description  
Features  
Y
Wide supply voltage range  
3.0V to 15V  
0.45 V typ.  
Employing complementary MOS (CMOS) transistors to  
achieve wide power supply operating range, low power con-  
sumption, and high noise margin, the CD4070BM/BC and  
CD4077BM/BC provide basic functions used in the imple-  
mentation of digital integrated circuit systems. The N- and  
P-channel enhancement mode transistors provide a sym-  
metrical circuit with output swing essentially equal to the  
supply voltage. No DC power other than that caused by  
leakage current is consumed during static condition. All in-  
puts are protected from damage due to static discharge by  
Y
High noise immunity  
DD  
Y
Low power TTL  
compatibility  
Fan out of 2 driving 74L  
or 1 driving 74LS  
Y
CD4070BÐPin compatible to CD4030A  
ÐEquivalent to MM54C86/MM74C86  
and MC14070B  
Y
CD4077BÐEquivalent to MC14077B  
diode clamps to V  
and V  
.
SS  
DD  
Connection Diagram  
CD4070BM/CD4070BC  
Dual-In-Line Package  
CD4077BM/CD4077BC  
Dual-In-Line Package  
TL/F/5976–1  
TL/F/5976–5  
Top View  
Top View  
Typical Performance  
Characteristics  
Truth Tables  
Propagation Delay Time  
vs Load Capacitance  
CD4070BM/CD4070BC  
CD4077BM/CD4077BC  
Inputs  
Outputs  
Y
Inputs  
Outputs  
Y
A
B
A
B
L
L
L
H
L
L
H
H
L
L
L
L
H
L
H
L
H
H
H
H
L
H
H
H
TL/F/5976–2  
C
1995 National Semiconductor Corporation  
TL/F/5976  
RRD-B30M105/Printed in U. S. A.  

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