Datasheet > CD4076BMS

CD4076BMS

更新时间： 2024-11-24 14:57:43

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
9页	353K
描述
CMOS 4 -Bit D-Type Register

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中文翻译

获取价格

技术参数
数据手册

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CD4076BMS 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
Reach Compliance Code：	compliant	风险等级：	5.65
Is Samacsys：	N	Base Number Matches：	1

CD4076BMS 数据手册

DATASHEET

CD4076BMS

CMOS 4 -Bit D-Type Registers

FN3325

Rev 0.00

December 1992

Features

Pinout

CD4076BMS

TOP VIEW

• High Voltage Type (20V Rating)

• Three State Outputs

• Input Disabled Without Gating the Clock

16 VDD

OUTPUT

DISABLE

• Gated Output Control Lines for Enabling or Disabling

the Outputs

15 RESET

14 DATA 1

13 DATA 2

12 DATA 3

11 DATA 4

• Standardized Symmetrical Output Characteristics

• 100% Tested for Quiescent Current at 20V

• Maximum Input Current of 1A at 18V Over Full Pack-

age Temperature Range; 100nA at 18V and +25^oC

DATA

INPUT

DISABLE

10 G2

CLOCK

VSS

• Noise Margin (Over Full Package/Temperature Range)

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

• 5V, 10V and 15V Parametric Ratings

Functional Diagram

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Specifications for Description of

‘B’ Series CMOS Devices”

DATA INPUT

DISABLE

OUTPUT

DISABLE

CLOCK

Description

CD4076BMS types are four-bit registers consisting of D-type

flip-flops that feature three-state outputs. Data Disable inputs

are provided to control the entry of data into the flip-flops.

When both Data Disable inputs are low, data at the D inputs

are loaded into their respective flip-flops on the next positive

transition of the clock input. Output Disable inputs are also

provided. When the Output Disable inputs are both low, the

normal logic states of the four outputs are available to the

load. The outputs are disabled independently of the clock by

a high logic level at either Output Disable input, and present

a high impedance.

4D - TYPE

FLIP-FLOPS

WITH

AND-OR

LOGIC

VSS = 8

VDD = 16

The CD4076BMS is supplied in these 16 lead outline pack-

ages:

RESET

Braze Seal DIP

Frit Seal DIP

H4T

H1E

H6W

Ceramic Flatpack

FN3325 Rev 0.00

December 1992

Page 1 of 9

12 3 4 5 6 7...9

中文翻译

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与CD4076BMS相关器件

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CD4076BMT	TI	获取价格	CMOS 4-BIT D-TYPE REGISTERS
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CD4076BMW	TI	获取价格	IC 4000/14000/40000 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDFP16, CERA
CD4076BMW/883	TI	获取价格	IC,FLIP-FLOP,QUAD,D TYPE,CMOS,FP,16PIN,CERAMIC
CD4076BMW/883B	NSC	获取价格	IC,FLIP-FLOP,QUAD,D TYPE,CMOS,FP,16PIN,CERAMIC
CD4076BMW/883B	TI	获取价格	IC,FLIP-FLOP,QUAD,D TYPE,CMOS,FP,16PIN,CERAMIC
CD4076BMW/883C	NSC	获取价格	IC,FLIP-FLOP,QUAD,D TYPE,CMOS,FP,16PIN,CERAMIC
CD4076BMW/883C	TI	获取价格	IC,FLIP-FLOP,QUAD,D TYPE,CMOS,FP,16PIN,CERAMIC
CD4076BMW-MIL	NSC	获取价格	IC,FLIP-FLOP,QUAD,D TYPE,CMOS,FP,16PIN,CERAMIC
CD4076BMW-MIL	TI	获取价格	IC,FLIP-FLOP,QUAD,D TYPE,CMOS,FP,16PIN,CERAMIC