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CD4041BMS PDF预览

CD4041BMS

更新时间: 2024-09-14 22:54:19
品牌 Logo 应用领域
英特矽尔 - INTERSIL /
页数 文件大小 规格书
7页 109K
描述
CMOS Quad True/Complement Buffer

CD4041BMS 数据手册

 浏览型号CD4041BMS的Datasheet PDF文件第2页浏览型号CD4041BMS的Datasheet PDF文件第3页浏览型号CD4041BMS的Datasheet PDF文件第4页浏览型号CD4041BMS的Datasheet PDF文件第5页浏览型号CD4041BMS的Datasheet PDF文件第6页浏览型号CD4041BMS的Datasheet PDF文件第7页 
CD4041UBMS  
Data Sheet  
December 1992  
File Number 3309  
CMOS Quad True/Complement Buffer  
Features  
• High Voltage Type (20V Rating)  
CD4041UBMS types are quad true/complement buffers con-  
sisting of n- and p- channel units having low channel resis-  
tance and high current (sourcing and sinking) capability. The  
CD4041UBMS is intended for use as a buffer, line driver, or  
CMOS-to-TTL driver. It can be used as an ultra-low power  
resistor-network driver for A/D and D/A conversion, as a  
transmission-line driver, and in other applications where high  
noise immunity and low power dissipation are primary  
design requirements.  
• Balanced Sink and Source Current; Approximately 4  
Times Standard “B” Drive  
• Equalized Delay to True and Complement Outputs  
• 100% Tested for Quiescent Current at 20V  
• Maximum Input Current of 1µA at 18V Over Full  
Package-Temperature Range;  
o
- 100nA at 18V and +25 C  
The CD4041UBMS is supplied in these 14 lead outline pack-  
ages:  
• 5V, 10V and 15V Parametric Ratings  
Braze Seal DIP  
Frit Seal DIP  
H4Q  
H1B  
• Meets All Requirements of JEDEC Tentative Standard  
No. 13B, “Standard Specificationsfor Description of  
‘B’ Series CMOS Devices”  
Ceramic Flatpack H3W  
Applications  
Pinout  
CD4041UBMS  
TOP VIEW  
• High Current Source/Sink Driver  
• CMOS-to-DTL/TTL Converter Buffer  
• Display Driver  
E = A  
F = A  
A
1
2
3
4
5
6
7
14 VDD  
13  
D
• MOS Clock Driver  
12 N = D  
11 M = D  
• Resistor Network Driver (Ladder or Weighted R)  
• Buffer  
G = B  
H = B  
B
10  
9
C
• Transmission Line Driver  
L = C  
K = C  
8
VSS  
Functional Diagram  
VDD  
VSS  
VDD  
VDD  
3
1
A
E
TRUE  
OUTPUT  
INPUT*  
E = A  
F = A  
2
F
VSS  
VSS  
VSS  
VDD  
6
4
B
G
P
N
G = B  
H = B  
COMPLEMENT  
OUTPUT  
5
H
*ALL INPUTS PROTECTED  
BY CMOS INPUT  
PROTECTION NETWORK  
10  
C
8
VDD  
VSS  
K
K = C  
L = C  
FIGURE 1. SCHEMATIC DIAGRAM 1 OF 4 BUFFERS  
9
L
13  
D
11  
M
M = D  
N = D  
VSS = 7  
VDD = 14  
12  
N
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
1

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