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CD4021BCM_NL PDF预览

CD4021BCM_NL

更新时间: 2024-11-04 19:54:03
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
7页 73K
描述
Parallel In Serial Out, 4000/14000/40000 Series, 8-Bit, Right Direction, True Output, CMOS, PDSO16, 0.150 INCH, MS-012, SOIC-16

CD4021BCM_NL 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP16,.25
针数:16Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.05
其他特性:OUTPUTS ALSO AVAILABLE AT 6TH AND 7TH STAGE OF THE SHIFT REGISTER计数方向:RIGHT
系列:4000/14000/40000JESD-30 代码:R-PDSO-G16
JESD-609代码:e3长度:9.9 mm
逻辑集成电路类型:PARALLEL IN SERIAL OUT最大频率@ Nom-Sup:2500000 Hz
湿度敏感等级:1位数:8
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:5/15 V
传播延迟(tpd):350 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Shift Registers
最大供电电压 (Vsup):15 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:3.9 mm最小 fmax:8 MHz
Base Number Matches:1

CD4021BCM_NL 数据手册

 浏览型号CD4021BCM_NL的Datasheet PDF文件第2页浏览型号CD4021BCM_NL的Datasheet PDF文件第3页浏览型号CD4021BCM_NL的Datasheet PDF文件第4页浏览型号CD4021BCM_NL的Datasheet PDF文件第5页浏览型号CD4021BCM_NL的Datasheet PDF文件第6页浏览型号CD4021BCM_NL的Datasheet PDF文件第7页 
October 1987  
Revised March 2002  
CD4021BC  
8-Stage Static Shift Register  
General Description  
Features  
The CD4021BC is an 8-stage parallel input/serial output  
shift register. A parallel/serial control input enables individ-  
ual JAM inputs to each of 8 stages. Q outputs are available  
from the sixth, seventh, and eighth stages. All outputs have  
equal source and sink current capabilities and conform to  
standard “B” series output drive.  
Wide supply voltage range: 3.0V to 15V  
High noise immunity: 0.45 VDD (typ.)  
Low power TTL compatibility:  
Fan out of 2 driving 74L or 1 driving 74LS  
5V–10V–15V parametric ratings  
Symmetrical output characteristics  
When the parallel/serial control input is in the logical “0”  
state, data is serially shifted into the register synchronously  
with the positive transition of the clock. When the parallel/  
serial control is in the logical “1” state, data is jammed into  
each stage of the register asynchronously with the clock.  
Maximum input leakage 1 µA at 15V over full tempera-  
ture range  
All inputs are protected against static discharge with diodes  
to VDD and VSS  
.
Ordering Code:  
Order Number  
CD4021BCM  
CD4021BCN  
Order Code  
Package Description  
M16A  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.  
Connection Diagram  
Truth Table  
CL  
Parallel/ PI 1 PI n  
Serial  
Control  
Qn  
(Note 2)  
Serial  
Q1  
(Internal)  
(Note 1)  
Input  
X
X
X
X
X
X
X
X
0
1
1
1
1
0
0
0
0
0
1
1
X
X
X
0
1
0
1
X
X
X
0
0
0
1
1
0
1
1
0
Qn1  
Qn1  
Qn  
1
1
X
Q1  
X = Don't care case  
Note 1: Level change  
Note 2: No change  
Top View  
© 2002 Fairchild Semiconductor Corporation  
DS005954  
www.fairchildsemi.com  

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