CD4021BCN_NL

更新时间： 2024-11-04 13:06:43

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		移位寄存器
页数	文件大小	规格书
7页	73K
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数据手册

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CD4021BCN_NL 数据手册

October 1987

Revised January 1999

CD4021BC

8-Stage Static Shift Register

All inputs are protected against static discharge with diodes

General Description

to V_DDand V_SS

The CD4021BC is an 8-stage parallel input/serial output

shift register. A parallel/serial control input enables individ-

ual JAM inputs to each of 8 stages. Q outputs are available

from the sixth, seventh, and eighth stages. All outputs have

equal source and sink current capabilities and conform to

standard “B” series output drive.

Features

■ Wide supply voltage range: 3.0V to 15V

■ High noise immunity: 0.45 V_DD(typ.)

■ Low power TTL compatibility:

When the parallel/serial control input is in the logical “0”

state, data is serially shifted into the register synchronously

with the positive transition of the clock. When the parallel/

serial control is in the logical “1” state, data is jammed into

each stage of the register asynchronously with the clock.

Fan out of 2 driving 74L or 1 driving 74LS

■ 5V–10V–15V parametric ratings

■ Symmetrical output characteristics

■ Maximum input leakage 1 µA at 15V over full tempera-

ture range

Ordering Code:

Order Number

CD4021BCM

CD4021BCN

Order Code

M16A

Package Description

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

N16E

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Truth Table

Parallel/

Serial PI 1 PI n

Control

Pin Assignments for DIP and SOIC

Q_n

(Note 2)

Serial

(Internal)

(Note 1) Input

Q_n−1

Q_n

X = Don't care case

Note 1: Level change

Note 2: No change

Top View

DS005954.prf

www.fairchildsemi.com

12 3 4 5 6 7

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