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CD4021BCMX PDF预览

CD4021BCMX

更新时间: 2024-11-03 23:40:23
品牌 Logo 应用领域
其他 - ETC 移位寄存器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
7页 77K
描述
SHIFT REGISTER|CMOS|SOP|16PIN|PLASTIC

CD4021BCMX 数据手册

 浏览型号CD4021BCMX的Datasheet PDF文件第2页浏览型号CD4021BCMX的Datasheet PDF文件第3页浏览型号CD4021BCMX的Datasheet PDF文件第4页浏览型号CD4021BCMX的Datasheet PDF文件第5页浏览型号CD4021BCMX的Datasheet PDF文件第6页浏览型号CD4021BCMX的Datasheet PDF文件第7页 
October 1987  
Revised March 2002  
CD4021BC  
8-Stage Static Shift Register  
General Description  
Features  
The CD4021BC is an 8-stage parallel input/serial output  
shift register. A parallel/serial control input enables individ-  
ual JAM inputs to each of 8 stages. Q outputs are available  
from the sixth, seventh, and eighth stages. All outputs have  
equal source and sink current capabilities and conform to  
standard “B” series output drive.  
Wide supply voltage range: 3.0V to 15V  
High noise immunity: 0.45 VDD (typ.)  
Low power TTL compatibility:  
Fan out of 2 driving 74L or 1 driving 74LS  
5V–10V–15V parametric ratings  
Symmetrical output characteristics  
When the parallel/serial control input is in the logical “0”  
state, data is serially shifted into the register synchronously  
with the positive transition of the clock. When the parallel/  
serial control is in the logical “1” state, data is jammed into  
each stage of the register asynchronously with the clock.  
Maximum input leakage 1 µA at 15V over full tempera-  
ture range  
All inputs are protected against static discharge with diodes  
to VDD and VSS  
.
Ordering Code:  
Order Number  
CD4021BCM  
CD4021BCN  
Order Code  
Package Description  
M16A  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.  
Connection Diagram  
Truth Table  
CL  
Parallel/ PI 1 PI n  
Serial  
Control  
Qn  
(Note 2)  
Serial  
Q1  
(Internal)  
(Note 1)  
Input  
X
X
X
X
X
X
X
X
0
1
1
1
1
0
0
0
0
0
1
1
X
X
X
0
1
0
1
X
X
X
0
0
0
1
1
0
1
1
0
Qn1  
Qn1  
Qn  
1
1
X
Q1  
X = Don't care case  
Note 1: Level change  
Note 2: No change  
Top View  
© 2002 Fairchild Semiconductor Corporation  
DS005954  
www.fairchildsemi.com  

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