Datasheet > CD4018BMS

CD4018BMS

更新时间： 2024-11-28 22:56:43

品牌	Logo	应用领域
英特矽尔 - INTERSIL		计数器
页数	文件大小	规格书
9页	88K
描述
CMOS Presettable Divide-By- “N” Counter

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CD4018BMS 数据手册

CD4018BMS

CMOS Presettable

Divide-By- “N” Counter

November 1994

Features

Description

• High Voltage Type (20V Rating)

CD4018BMS types consist of 5 Johnson-Counter stages,

buffered Q outputs from each stage, and counter preset con-

trol gating. CLOCK, RESET, DATA, PRESET ENABLE, and

5 individual JAM inputs are provided. Divide by 10, 8, 6, 4, or

2 counter conﬁgurations can be implemented by feeding the

Q5, Q4, Q3, Q2, Q1 signals, respectively, back to the DATA

input. Divide-by-9, 7, 5, or 3 counter conﬁgurations can be

implemented by the use of a CD4011B to gate the feedback

connection to the DATA input. Divide-by functions greater

than 10 can be achieved by use of multiple CD4018BMS

units. The counter is advanced one count at the positive

clock-signal transition. Schmitt Trigger action on the clock

line permits unlimited clock rise and fall times. A high

RESET signal clears the counter to an all-zero condition. A

high PRESET-ENABLE signal allows information on the JAM

inputs to preset the counter. Anti-lock gating is provided to

assure the proper counting sequence.

• Medium Speed Operation 10MHz (typ.) at VDD - VSS =

10V

• Fully Static Operation

• 100% Tested for Quiescent Current at 20V

• Standardized Symmetrical Output Characteristics

• 5V, 10V and 15V Parametric Ratings

• Maximum Input Current of 1µa at 18V Over Full Pack-

age-Temperature Range;

- 100nA at 18V and 25^oC

• Noise Margin (Over Full Package Temperature Range):

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

The CD4018BMS is supplied in these 16-lead outline pack-

ages:

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Speciﬁcations for Description of

‘B’ Series CMOS Devices”

Braze Seal DIP

Frit Seal DIP

H4T

H1F

Applications

Ceramic Flatpack H6W

• Fixed and Programmable Divided- By-10, 9, 8, 7, 6, 5,

4, 3, 2 Counters

• Fixed and Programmable Counters Greater Than 10

• Programmable Decade Counters

• Divide-By- “N” Counters/Frequency Synthesizers

• Frequency Division

Functional Diagram

VDD

JAM INPUTS

“2” “4”

“1”

“3”

“5”

• Counter Control/Timers

12 16

PRESET

ENABLE

Pinout

CLOCK

CD4018BMS

TOP VIEW

DATA

JAM 1

JAM 2

16 VDD

RESET

15 RESET

14 CLOCK

13 Q5

12 JAM 5

11 Q4

VSS

10 PRESET ENABLE

JAM 3

VSS

JAM 4

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 3298

7-350

12 3 4 5 6 7...9

中文翻译

下载PDF

与CD4018BMS相关器件

型号	品牌	获取价格	描述	数据表
CD4018BMT	TI	获取价格	CMOS PRESETTABLE DIVIDE-BY-N COUNTER
CD4018BMTE4	TI	获取价格	CMOS Presettable Divide-By-N Counter 16-SOIC -55 to 125
CD4018BMTG4	TI	获取价格	4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 5-BIT UP RING COUNTER, PDSO16, GREEN,
CD4018BMW	ETC	获取价格	Johnson Counter
CD4018BMW/883	ETC	获取价格	Johnson Counter
CD4018BMW/883B	TI	获取价格	IC,COUNTER,UP,DECADE,CMOS,FP,16PIN,CERAMIC
CD4018BMW/883C	TI	获取价格	IC,COUNTER,UP,DECADE,CMOS,FP,16PIN,CERAMIC
CD4018BNSR	TI	获取价格	CMOS PRESETTABLE DIVIDE-BY-N COUNTER
CD4018BNSRG4	TI	获取价格	4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 5-BIT UP RING COUNTER, PDSO16, GREEN,
CD4018BNSRG4	ROCHESTER	获取价格	Ring Counter, 4000/14000/40000 Series, Synchronous, Positive Edge Triggered, 5-Bit, Up Dir

与CD4018BMS相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

51
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

41
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

69
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

65

产品中心

服务支持

精选活动

关于我们

帮助中心

CD4018BMS

CD4018BMS 数据手册

与CD4018BMS相关器件

与CD4018BMS相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CD4018BMS

CD4018BMS 数据手册

与CD4018BMS相关器件

与CD4018BMS相关文章

您还可以找

您在本页遇到什么问题？