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CD40192 PDF预览

CD40192

更新时间: 2024-11-28 22:56:43
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英特矽尔 - INTERSIL 计数器时钟
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12页 152K
描述
CMOS Presettable Up/Down Counters (Dual Clock With Reset)

CD40192 数据手册

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CD40192BMS  
CD40193BMS  
CMOS Presettable Up/Down Counters  
(Dual Clock With Reset)  
December 1992  
Features  
Description  
• CD40192BMS - BCD Type  
• CD40193BMS - Binary Type  
• High Voltage Type (20V Rating)  
CD40192BMS Presettable BCD Up/Down Counter and the  
CD40193BMS Presettable Binary Up/Down Counter each con-  
sist of 4 synchronously clocked, gated “D” type flip-flops con-  
nected as a counter. The inputs consist of 4 individual jam lines,  
a PRESET ENABLE control, individual CLOCK UP and  
CLOCK DOWN signals and a master RESET. Four buffered Q  
signal outputs as well as CARRY and BORROW outputs for  
multiple-stage counting schemes are provided.  
• Individual Clock Lines for Counting Up or Counting  
Down  
• Synchronous High-Speed Carry and Borrow Propaga-  
tion Delays for Cascading  
The counter is cleared so that all outputs are in a low state by a  
high on the RESET line. A RESET is accomplished asynchro-  
nously with the clock. Each output is individually programmable  
asynchronously with the clock to the level on the corresponding  
jam input when the PRESET ENABLE control is low.  
• Asynchronous Reset and Preset Capability  
• Medium Speed Operation  
- fCL = 8MHz (typ.) at 10V  
• 5V, 10V and 15V Parametric Ratings  
• Standardize Symmetrical Output Characteristics  
• 100% Tested for Quiescent Current at 20V  
The counter counts up one count on the positive clock edge of  
the CLOCK UP signal provided the CLOCK DOWN line is high.  
The counter counts down one count on the positive clock edge  
of the CLOCK DOWN signal provided the CLOCK UP line is  
high.  
• Maximum Input Current of 1µA at 18V Over Full Pack-  
age Temperature Range; 100nA at 18V and +25oC  
• Noise Margin (Over Full Package/Temperature Range)  
- 1V at VDD = 5V  
The CARRY and BORROW signals are high when the counter  
is counting up or down. The CARRY signal goes low one-half  
clock cycle after the counter reaches its maximum count in the  
count-up mode. The BORROW signal goes low one-half clock  
cycle after the counter reaches its minimum count in the count-  
down mode. Cascading of multiple packages is easily accom-  
plished without the need for additional external circuitry by tying  
the BORROW and CARRY outputs to the CLOCK DOWN and  
CLOCK UP inputs, respectively, of the succeeding counter  
package.  
- 2V at VDD = 10V  
- 2.5V at VDD = 15V  
• Meets All Requirements of JEDEC Tentative Standard  
No. 13B, “Standard Specifications for Description of  
‘B’ Series CMOS Devices”  
Applications  
• Up/Down Difference Counting  
• Multistage Ripple Counting  
• Synchronous Frequency Dividers  
• A/D and D/A Conversion  
The CD40192BMS and CD40193BMS are supplied in these  
16-lead outline packages:  
Braze Seal DIP  
Frit Seal DIP  
*H4W, †H4X  
H1F  
Ceramic Flatpack  
* CD40192B Only  
*H6P,  
†CD40193B Only  
†H6W  
• Programmable Binary or BCD Counting  
Functional Diagram  
Pinout  
CD40192BMS, CD40193BMS  
PRESET  
ENABLE  
TOP VIEW  
11  
15  
J1  
3
2
J2  
Q2  
Q1  
1
2
3
4
5
6
7
8
16 VDD  
Q1  
1
Q2  
15 J1  
J2  
6
10  
Q3  
14 RESET  
13 BORROW  
12 CARRY  
11 PRESET ENABLE  
10 J3  
J3  
7
9
Q4  
J4  
CLOCK DOWN  
CLOCK UP  
13  
12  
5
CLOCK UP  
4
BORROW  
CARRY  
CLOCK DOWN  
Q3  
Q4  
14  
VDD = 16  
VSS = 8  
RESET  
9
J4  
VSS  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 3363  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
7-1419  

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