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CD40192BCN PDF预览

CD40192BCN

更新时间: 2024-11-29 22:56:43
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 计数器
页数 文件大小 规格书
7页 77K
描述
Synchronous 4-Bit Up/Down Decade Counter . Synchronous 4-Bit Up/Down Binary Counter

CD40192BCN 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP16,.3
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.45
其他特性:TCO UP AND TCO DOWN OUTPUTS; SEPARATE UP/DOWN CLOCK计数方向:BIDIRECTIONAL
系列:4000/14000/40000JESD-30 代码:R-PDIP-T16
JESD-609代码:e0长度:19.305 mm
负载电容(CL):50 pF负载/预设输入:YES
逻辑集成电路类型:DECADE COUNTER最大频率@ Nom-Sup:2500000 Hz
工作模式:SYNCHRONOUS位数:4
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5/15 V传播延迟(tpd):400 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Counters最大供电电压 (Vsup):15 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:7.62 mm
最小 fmax:7.5 MHzBase Number Matches:1

CD40192BCN 数据手册

 浏览型号CD40192BCN的Datasheet PDF文件第2页浏览型号CD40192BCN的Datasheet PDF文件第3页浏览型号CD40192BCN的Datasheet PDF文件第4页浏览型号CD40192BCN的Datasheet PDF文件第5页浏览型号CD40192BCN的Datasheet PDF文件第6页浏览型号CD40192BCN的Datasheet PDF文件第7页 
October 1987  
Revised January 1999  
CD40192BC • CD40193BC  
Synchronous 4-Bit Up/Down Decade Counter •  
Synchronous 4-Bit Up/Down Binary Counter  
All inputs are protected against damage due to static dis-  
General Description  
The CD40192BC and CD40193BC up/down counters are  
charge by clamps to VDD and VSS  
.
monolithic complementary MOS (CMOS) integrated cir-  
Features  
Wide supply voltage range: 3V to 15V  
cuits. The CD40192BC is  
a BCD counter, while the  
CD40193BC is a binary counter.  
Counting up and counting down is performed by two count  
inputs, one being held HIGH while the other is clocked. The  
outputs change on the positive-going transition of this  
clock.  
High noise immunity: 0.45 VDD (typ.)  
Low power TTL compatibility: Fan out of 2 driving 74L  
or 1 driving 74LS  
Carry and borrow outputs for easy expansion to N-bit by  
cascading  
These counters feature preset inputs that are enabled  
when load is a logical “0” and a clear which forces all out-  
puts to “0” when it is at logical “1”. The counters also have  
carry and borrow outputs so that they can be cascaded  
using no external circuitry.  
Asynchronous clear  
Equivalent to: MM74C192 and MM74C193  
Ordering Code:  
Order Number Package Number  
Package Description  
CD40192BCN  
CD40193BCN  
CD40193BCM  
N16E  
N16E  
M16A  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Connection Diagram  
Cascading Packages  
Pin Assignments for DIP and SOIC  
Top View  
© 1999 Fairchild Semiconductor Corporation  
DS005988.prf  
www.fairchildsemi.com  

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