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CD40175BM PDF预览

CD40175BM

更新时间: 2024-11-14 22:56:43
品牌 Logo 应用领域
美国国家半导体 - NSC 触发器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 137K
描述
Hex D Flip-Flop

CD40175BM 数据手册

 浏览型号CD40175BM的Datasheet PDF文件第2页浏览型号CD40175BM的Datasheet PDF文件第3页浏览型号CD40175BM的Datasheet PDF文件第4页浏览型号CD40175BM的Datasheet PDF文件第5页浏览型号CD40175BM的Datasheet PDF文件第6页 
February 1988  
CD40174BM/CD40174BC Hex D Flip-Flop  
CD40175BM/CD40175BC Quad D Flip-Flop  
General Description  
The CD40174B consists of six positive-edge triggered  
D-type flip-flops; the true outputs from each flip-flop are ex-  
ternally available. The CD40175B consists of four positive-  
edge triggered D-type flip-flops; both the true and comple-  
ment outputs from each flip-flop are externally available.  
All inputs are protected from static discharge by diode  
clamps to V and V  
.
SS  
DD  
Features  
Y
Wide supply voltage range  
High noise immunity  
Low power TTL  
3V to 15V  
0.45 V (typ.)  
All flip-flops are controlled by a common clock and a com-  
mon clear. Information at the D inputs meeting the set-up  
time requirements is transferred to the Q outputs on the  
positive-going edge of the clock pulse. The clearing opera-  
tion, enabled by a negative pulse at Clear input, clears all Q  
outputs to logical ‘‘0’’ and Qs (CD40175B only) to logical ‘‘1’’.  
Y
Y
DD  
fan out of 2 driving 74L  
or 1 driving 74 LS  
compatibility  
Y
Y
Equivalent to MC14174B, MC14175B  
Equivalent to MM74C174, MM74C175  
Connection Diagrams  
CD40174B  
Dual-In-Line Package  
CD40175B  
Dual-In-Line Package  
TL/F/5987–1  
TL/F/5987–2  
Top View  
Top View  
Order Number CD40174B or CD40175B  
Truth Table  
Inputs  
Clock  
Outputs  
Clear  
D
Q
Q*  
L
H
H
H
H
X
u
u
H
X
H
L
L
H
H
L
L
H
X
X
NC  
NC  
NC  
NC  
L
e
e
e
e
e
e
H
High level  
Low level  
Irrelevant  
L
X
Transition from low to high level  
No change  
u
NC  
*
Q for CD40175B only  
C
1995 National Semiconductor Corporation  
TL/F/5987  
RRD-B30M105/Printed in U. S. A.  

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