Datasheet > CD40175BMS

CD40175BMS

更新时间： 2024-11-14 22:56:43

品牌	Logo	应用领域
英特矽尔 - INTERSIL		触发器
页数	文件大小	规格书
8页	64K
描述
CMOS Quad ‘D’ Type Flip-Flop

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中文翻译

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数据手册

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CD40175BMS 数据手册

CD40175BMS

CMOS Quad ‘D’ Type Flip-Flop

December 1992

Features

Pinout

CD40175BMS

TOP VIEW

• High Voltage Type (20V Rating)

• Output Compatible with Two HTL Loads, Two Low Power

TTL Loads, or One Low Power Schottky TTL Load

CLEAR

16 VDD

15 Q4

14 Q4

13 D4

12 D3

11 Q3

10 Q3

• Functional Equivalent to TTL74175

• 100% Tested for Quiescent Current at 20V

• 5V, 10V and 15V Parametric Ratings

• Maximum Input Current of 1µA at 18V Over Full Pack-

age Temperature Range; 100nA at 18V and +25^oC

• Noise Margin (Over Full Package/Temperature Range)

- 1V at VDD = 5V

CLOCK

VSS

- 2V at VDD = 10V

VDD = PIN 16

VSS = PIN 8

- 2.5V at VDD = 15V

• Standardized Symmetrical Output Characteristics

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Speciﬁcations for Description of

‘B’ Series CMOS Devices”

Functional Diagram

Applications

• Shift Registers

F/F1

F/F2

• Buffer/Storage Registers

• Pattern Generators

Description

CD40175BMS consists of four identical D-type ﬂip-ﬂops.

Each ﬂip-ﬂop has an independent DATA D input and comple-

mentary Q and Q outputs. The CLOCK and CLEAR inputs

are common to all ﬂip-ﬂops. Data are transferred to the Q

outputs on the positive going transition of the clock pulse. All

four ﬂip-ﬂops are simultaneously reset by a low level on the

CLEAR input.

F/F3

F/F4

These devices can function as shift register elements or as

T-type ﬂip-ﬂops for toggle and counter applications.

CLOCK

VSS = 8

VDD = 16

CLEAR

The CD40175BMS is supplied in these 16-lead outline

packages:

Braze Seal DIP

H4T

Ceramic Flatpack

H6W

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 3360

7-1392

12 3 4 5 6 7 8

中文翻译

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