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CD4017BC

更新时间: 2024-10-01 22:56:43
品牌 Logo 应用领域
美国国家半导体 - NSC 计数器
页数 文件大小 规格书
8页 168K
描述
Decade Counter/Divider with 10 Decoded Outputs

CD4017BC 数据手册

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March 1988  
CD4017BM/CD4017BC Decade Counter/Divider  
with 10 Decoded Outputs  
CD4022BM/CD4022BC Divide-by-8 Counter/Divider  
with 8 Decoded Outputs  
General Description  
The CD4017BM/CD4017BC is a 5-stage divide-by-10 John-  
son counter with 10 decoded outputs and a carry out bit.  
Features  
Y
Wide supply voltage range  
3.0V to 15V  
0.45 V (typ.)  
Y
High noise immunity  
DD  
Y
Low power  
TTL compatibility  
Fan out of 2 driving 74L  
or 1 driving 74LS  
The CD4022BM/CD4022BC is a 4-stage divide-by-8 John-  
son counter with 8 decoded outputs and a carry-out bit.  
Y
Medium speed operation  
5.0 MHz (typ.)  
with 10V V  
DD  
These counters are cleared to their zero count by a logical  
‘‘1’’ on their reset line. These counters are advanced on the  
positive edge of the clock signal when the clock enable sig-  
nal is in the logical ‘‘0’’ state.  
Y
Low power  
10 mW (typ.)  
Y
Fully static operation  
The configuration of the CD4017BM/CD4017BC and  
CD4022BM/CD4022BC permits medium speed operation  
and assures a hazard free counting sequence. The 10/8  
decoded outputs are normally in the logical ‘‘0’’ state and go  
to the logical ‘‘1’’ state only at their respective time slot.  
Each decoded output remains high for 1 full clock cycle.  
The carry-out signal completes a full cycle for every 10/8  
clock input cycles and is used as a ripple carry signal to any  
succeeding stages.  
Applications  
Y
Automotive  
Y
Instrumentation  
Y
Medical electronics  
Y
Alarm systems  
Y
Industrial electronics  
Y
Remote metering  
Connection Diagrams  
CD4017B  
Dual-In-Line Package  
CD4022B  
Dual-In-Line Package  
TL/F/5950–1  
TL/F/5950–2  
Top View  
Top View  
Order Number CD4017B or CD4022B  
C
1995 National Semiconductor Corporation  
TL/F/5950  
RRD-B30M105/Printed in U. S. A.  

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