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CD4017BDMS

更新时间： 2024-11-15 14:41:23
品牌 Logo 应用领域
瑞萨 - RENESAS 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
10页 156K
描述
4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 10-BIT UP RING COUNTER, PDIP16

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中文翻译

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CD4017BDMS 技术参数

生命周期：Obsolete包装说明：,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.04其他特性：JOHNSON COUNTER WITH 10 DECODED OUTPUTS
计数方向：UP系列：4000/14000/40000
JESD-30 代码：R-PDIP-T16负载电容（CL）：50 pF
负载/预设输入：YES逻辑集成电路类型：RING COUNTER
工作模式：SYNCHRONOUS位数：10
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：PLASTIC/EPOXY封装形状：RECTANGULAR
封装形式：IN-LINE传播延迟（tpd）：878 ns
认证状态：Not Qualified表面贴装：NO
技术：CMOS温度等级：MILITARY
端子形式：THROUGH-HOLE端子位置：DUAL
触发器类型：POSITIVE EDGE最小 fmax：10 MHz
Base Number Matches：1

CD4017BDMS 数据手册

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CD4017BMS, CD4022BMS  
Data Sheet  
August 1998  
File Number 3297  
CMOS Counter/Dividers  
Features  
• High Voltage Types (20V Rating)  
CD4017BMS - Decade Counter with 10 Decoded Outputs  
CD4022BMS - Octal Counter with 8 Decoded Outputs  
• Fully Static Operation  
• Medium-Speed Operation 10MHz (Typ) at VDD = 10V  
• Standardized Symmetrical Output Characteristics  
• 100% Tested for Quiescent Current at 20V  
• 5V, 10V and 15V Parametric Ratings  
CD4017BMS and CD4022BMS are 5-stage and 4-stage  
Johnson counters having 10 and 8 decoded outputs, respec-  
tively. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT  
signal. Schmitt trigger action in the CLOCK input circuit provides  
pulse shaping that allows unlimited clock input pulse rise and fall  
times.  
• Meets All Requirements of JEDEC Tentative Standard  
Number 13A, “Standard Specifications for Description  
of ‘B’ Series CMOS Devices”  
These counters are advanced one count at the positive clock sig-  
nal transition if the CLOCK INHIBIT signal is low. Counter  
advancement via the clock line is inhibited when the CLOCK  
INHIBIT signal is high. A high RESET signal clears the counter to  
its zero count. Use of the Johnson counter configuration permits  
high speed operation, 2-input decode gating and spike-free  
decoded outputs. Anti-lock gating is provided, thus assuring  
proper counter sequence. The decoded output are normally low  
and go high only at their respective decoded time slot. Each  
decoded output remains high for one full clock cycle. A CARRY-  
OUT signal completes one cycle every 10 clock input cycles in  
the CD4017BMS or every 8 clock input cycles in the  
CD4022BMS and is used to ripple-clock the succeeding device  
in a multi-device counting chain.  
Applications  
• Decade Counter/Decimal Decode Display (CD4017BMS)  
• Binary Counter/Decoder  
• Frequency Division  
• Counter Control/Timers  
• Divide-by-N Counting  
• For Further Application Information, See ICAN-6166  
“COS/MOS MSI Counter and Register Design and  
Applications”  
The CD4017BMS and CD4022BMS series types are supplied in  
these 16 lead outline packages  
Pinouts  
CD4017BMS  
TOP VIEW  
Braze Seal DIP  
Frit Seal DIP  
*H4W †H4X  
*H1F  
H6W  
†H1E  
5
1
2
3
4
5
6
7
8
16 VDD  
Ceramic Flatpack  
*CD4017B Only  
1
15 RESET  
14 CLOCK  
13 CLOCK INHIBIT  
12 CARRY OUT  
11 9  
† CD4022B Only  
0
Functional Diagrams  
2
6
CD4017BMS  
7
CLOCK  
CLOCK INHIBIT  
RESET  
14  
13  
15  
“0”  
“1”  
“2”  
“3”  
“4”  
“5”  
“6”  
“7”  
“8”  
“9”  
3
2
4
7
10  
1
5
6
9
11  
12  
10 4  
3
NC = NO  
CONNECTION  
9
8
VSS  
DECODED  
DECIMAL  
OUT  
VCC = 16  
VSS = 8  
CD4022BMS  
TOP VIEW  
CARRY OUT  
1
0
1
2
3
4
5
6
7
8
16 VDD  
CD4022BMS  
15 RESET  
14 CLOCK  
13 CLOCK INHIBIT  
12 CARRY OUT  
11 4  
2
CLOCK  
CLOCK INHIBIT  
RESET  
14  
13  
15  
“0”  
“1”  
“2”  
“3”  
“4”  
“5”  
“6”  
“7”  
2
1
3
7
11  
4
5
10  
12  
5
6
DECODED  
OUT  
NC  
3
10 7  
NC = NO  
CONNECTION  
VCC = 16  
VSS = 8  
9
NC  
VSS  
CARRY OUT  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
1
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