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CD22402E

更新时间： 2024-09-13 06:47:03
品牌 Logo 应用领域
哈里斯 - HARRIS 商用集成电路电视光电二极管电机
页数 文件大小 规格书
11页 79K
描述
Sync Generator for TV Applications and Video Processing Systems

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中文翻译

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CD22402E 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：DIP, DIP24,.6Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.8
商用集成电路类型：CONSUMER CIRCUITJESD-30 代码：R-PDIP-T24
JESD-609代码：e0端子数量：24
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP24,.6封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5/15 V认证状态：Not Qualified
子类别：Other Consumer ICs最大压摆率：5 mA
最大供电电压 (Vsup)：15 V最小供电电压 (Vsup)：4 V
表面贴装：NO技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED

CD22402E 数据手册

 浏览型号CD22402E的Datasheet PDF文件第2页浏览型号CD22402E的Datasheet PDF文件第3页浏览型号CD22402E的Datasheet PDF文件第4页浏览型号CD22402E的Datasheet PDF文件第5页浏览型号CD22402E的Datasheet PDF文件第6页浏览型号CD22402E的Datasheet PDF文件第7页 
Semiconductor  
CD22402  
Sync Generator for TV Applications  
and Video Processing Systems  
May 1999  
Features  
Description  
• Interlaced Composite Sync Output  
• Automatic Genlock Capability  
• Crystal Oscillator Operation  
The Harris CD22402 (Note) is a CMOS LSI sync generator that  
produces all the timing signals required to drive a fully 2-to-1  
interlaced 525-line 30-frame/second, or 625-line 25-frame/sec-  
ond TV camera or video processing system. A complete sync  
waveform is produced which begins each field with six serrated  
vertical sync pulses, preceded and followed by six half-width  
double frequency equalizing pulses. The sync output is gated by  
the master clock to preserve horizontal phase continuity during  
the vertical interval.  
[ /Title  
(CD2240  
2)  
/Subject  
(Sync  
Genera-  
tor for  
TV  
Applica-  
tions and  
Video  
• 525 or 625 Line Operation  
• Vertical Reset Option  
• Wide Power Supply Operating Voltage . . . . . 4V to 15V  
Applications  
• Cameras  
The CD22402 can be operated either in “genlock” mode, in  
which it is synchronized with a reference sync pulse train from  
another TV camera, or in “stand-alone” mode, in which it is syn-  
chronized with a local on-chip crystal oscillator (the crystal and  
two passive components are off chip). Also, the circuit can  
sense the presence or absence of a reference sync pulse train  
and automatically select the “genlock” or “stand-alone” mode.  
• Monitors and Displays  
• CATV  
• Teletext  
• Video Games  
• Sync Restorer  
• Video Service Instruments  
Process-  
A frame sync pulse is produced at the beginning of every odd  
field. The vertical counter can be reset to either the first equalizing  
pulse or the first vertical sync pulse of the vertical interval. The  
interlaced sync provided by the CD22402 differs from RS-170 by  
having slightly narrower sync and equalizing pulses. The clock  
frequency of 32 times horizontal rate allows for approximately 4µs  
horizontal pulse widths and 2µs equalizing pulses. Otherwise  
operation can be phase locked to a color sub-carrier for a full  
interlaced operating system.  
Part Number Information  
TEMP.  
PKG.  
NO.  
o
PART NUMBER RANGE ( C)  
PACKAGE  
-55 to 125 24 Ld SBDIP  
-40 to 85 24 Ld PDIP  
CD22402D  
CD22402E  
D24.6  
E24.6  
The CD22402 is operable with a single supply over a voltage  
range of 4V to 15V.  
Pinout  
CD22402 (PDIP, SBDIP)  
TOP VIEW  
1
24 RESISTOR CONNECTION FOR GENLOCK OSCILLATOR  
23 MASTER FREQUENCY INPUT  
DELAY, GENLOCK TO CRYSTAL OSCILLATOR  
CRYSTAL OSCILLATOR FEEDBACK TAP  
2
3
V
22  
21  
R-C CONNECTION FOR GENLOCK OSCILLATOR  
DELAY, GENLOCK TO CRYSTAL OSCILLATOR  
SS  
HORIZONTAL DRIVE OUTPUT  
MIXED SYNC OUTPUT  
4
5
20 GENLOCK INPUT (COMPOSITE SYNC)  
19  
6
GENLOCK OSCILLATOR CAPACITOR CONNECTION  
MIXED BEAM BLANKING OUTPUT  
V
DD  
7
18  
17 VERTICAL PROCESSING BLANKING OUTPUT  
16  
525 LINE TO 625 LINE OPERATION SWITCH  
8
VERTICAL COUNTER RESET TO FIRST EQUALIZING PULSE  
VERTICAL DRIVE OUTPUT  
9
SHORT VERTICAL DRIVE OUTPUT  
10  
11  
12  
15 FRAME SYNC OUTPUT (ODD FIELD)  
VERTICAL RESET TO FIRST VERTICAL SYNC PULSE  
HORIZONTAL CLAMP OUTPUT  
14 HORIZONTAL PROCESSING BLANKING OUTPUT  
13 MIXED PROCESSING BLANKING OUTPUT  
V
SS  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
File Number 1686.5  
Copyright © Harris Corporation 1999  
8-40  
1234567...11

中文翻译

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