Datasheet > CAT9954AWI-T2

CAT9954AWI-T2

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
CATALYST		/
页数	文件大小	规格书
16页	267K
描述
8-bit I2C and SMBus I/O Port with Interrupt

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中文翻译

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数据手册

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CAT9954AWI-T2 数据手册

CAT9554, CAT9554A

The command byte is the first byte to follow the device

address byte during a write/read bus transaction. The

which register will be written or read.

Acknowledge

After a successful data transfer, each receiving device

is required to generate an acknowledge. The

acknowledging device pulls down the SDA line during

the ninth clock cycle, signaling that it received the 8 bits

of data. The SDA line remains stable LOW during the

HIGH period of the acknowledge related clock pulse

(Figure 5).

The input port register is a read only port. It reflects the

incoming logic levels of the I/O pins, regardless of

whether the pin is defined as an input or an output by the

configuration register. Writes to the input port register

are ignored.

The CAT9554/9554A respond with an acknowledge

afterreceivingaSTARTconditionanditsslaveaddress.

If the device has been selected along with a write

operation, it responds with an acknowledge after

receiving each 8-bit byte.

Table 2. Register 0 – Input Port Register

bit

default

When the CAT9554/9554A begins a READ mode it

transmits 8 bits of data, releases the SDA line, and

monitors the line for an acknowledge. Once it receives

this acknowledge, the CAT9554/9554A will continue to

transmit data. If no acknowledge is sent by the Master,

the device terminates data transmission and waits for a

STOP condition. The master must then issue a STOP

condition to return the CAT9554/9554A to the standby

power mode and place the device in a known state.

Table 3. Register 1 – Output Port Register

bit

default

Table 4. Register 2 – Polarity Inversion Register

Registers and Bus Transactions

The CAT9554/9554A consist of an input port register,

an output port register, a polarity inversion register and

a configuration register. Table 1 shows the register

address table. Tables 2 to 5 list Register 0 through

bit

default

Table 5. Register 3 – Configuration Register

Table 1. Register Command Byte

bit

Command

(hex)

Protocol

Function

default

0x00

0x01

Read byte

Input port register

Output port register

Read/write byte

0x02

0x03

Read/write byte

Polarity inversion register

Configuration register

BUS RELEASE DELAY (TRANSMITTER)

BUS RELEASE DELAY (RECEIVER)

SCL FROM

MASTER

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

ACK SETUP

START

ACK DELAY

Figure 8. Acknowledge Timing

Characteristics subject to change without notice

Doc. No. 25088, Rev. B

1...6 7 8910 11 12...16

中文翻译

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与CAT9954AWI-T2相关器件

型号	品牌	获取价格	描述	数据表
CAT9954AYI-G-T2	CATALYST	获取价格	8-bit I2C and SMBus I/O Port with Interrupt
CAT9954AYI-T2	CATALYST	获取价格	8-bit I2C and SMBus I/O Port with Interrupt
CAT9954HV4I-G-T2	CATALYST	获取价格	8-bit I2C and SMBus I/O Port with Interrupt
CAT9954HV4I-T2	CATALYST	获取价格	8-bit I2C and SMBus I/O Port with Interrupt
CAT9954WI-G-T2	CATALYST	获取价格	8-bit I2C and SMBus I/O Port with Interrupt
CAT9954WI-T2	CATALYST	获取价格	8-bit I2C and SMBus I/O Port with Interrupt
CAT9954YI-G-T2	CATALYST	获取价格	8-bit I2C and SMBus I/O Port with Interrupt
CAT9954YI-T2	CATALYST	获取价格	8-bit I2C and SMBus I/O Port with Interrupt
CATA6B3	ETC	获取价格	Ceramic Surface Mount TCXO
CATABB3	ETC	获取价格	Ceramic Surface Mount TCXO

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