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CAT9954AWI-T2 PDF预览

CAT9954AWI-T2

更新时间: 2022-04-23 23:00:11
品牌 Logo 应用领域
CATALYST /
页数 文件大小 规格书
16页 267K
描述
8-bit I2C and SMBus I/O Port with Interrupt

CAT9954AWI-T2 数据手册

 浏览型号CAT9954AWI-T2的Datasheet PDF文件第4页浏览型号CAT9954AWI-T2的Datasheet PDF文件第5页浏览型号CAT9954AWI-T2的Datasheet PDF文件第6页浏览型号CAT9954AWI-T2的Datasheet PDF文件第8页浏览型号CAT9954AWI-T2的Datasheet PDF文件第9页浏览型号CAT9954AWI-T2的Datasheet PDF文件第10页 
CAT9554, CAT9554A  
INT: Interrupt Output  
The open-drain interrupt output is activated when one of  
the port pins configured as an input changes state  
(differs from the corresponding input port register bit  
state).Theinterruptisdeactivatedwhentheinputreturns  
to its previous state or the input port register is read.  
Changing an I/O from an output to an input may cause  
a false interrupt if the state of the pin does not match the  
contents of the input port register.  
Data from  
Shift Register  
Output Port  
Register Data  
Configuration  
Register  
Data from  
Shift Register  
D
Q
V
CC  
FF  
Q1  
Write  
Configuration Pulse  
C
Q
K
D
C
Q
FF  
I/O to I/O  
0
7
Write Pulse  
Q
K
Output Port  
Register  
Q2  
Input Port  
Register  
V
SS  
D
Q
Input Port  
Register Data  
LATCH  
Read Pulse  
C
K
Q
To INT  
Data from  
Shift Register  
Polarity  
Register Data  
D
C
Q
FF  
Write  
Polarity  
Register  
Q
K
Polarity  
Inversion Register  
Figure 4. Simplified Schematic of I/O to I/O  
0
7
© 2006 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Doc. No. 25088, Rev. B  
7

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