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CAT22C10WE-30 PDF预览

CAT22C10WE-30

更新时间: 2024-10-28 20:10:27
品牌 Logo 应用领域
安森美 - ONSEMI 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
10页 70K
描述
IC,NOVRAM,64X4,CMOS,SOP,16PIN,PLASTIC

CAT22C10WE-30 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:SOP, SOP16,.4Reach Compliance Code:compliant
风险等级:5.8最长访问时间:300 ns
JESD-30 代码:R-PDSO-G16内存集成电路类型:NON-VOLATILE SRAM
内存宽度:4端子数量:16
字数:64 words字数代码:64
最高工作温度:125 °C最低工作温度:-40 °C
组织:64X4封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
电源:5 V认证状态:Not Qualified
最大待机电流:0.00003 A子类别:SRAMs
最大压摆率:0.04 mA标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
Base Number Matches:1

CAT22C10WE-30 数据手册

 浏览型号CAT22C10WE-30的Datasheet PDF文件第2页浏览型号CAT22C10WE-30的Datasheet PDF文件第3页浏览型号CAT22C10WE-30的Datasheet PDF文件第4页浏览型号CAT22C10WE-30的Datasheet PDF文件第5页浏览型号CAT22C10WE-30的Datasheet PDF文件第6页浏览型号CAT22C10WE-30的Datasheet PDF文件第7页 
E
CAT22C10  
256-Bit Nonvolatile CMOS Static RAM  
TM  
FEATURES  
Single 5V Supply  
Low CMOS Power Consumption:  
–Active: 40mA Max.  
Fast RAM Access Times:  
–Standby: 30µA Max.  
–200ns  
–300ns  
JEDEC Standard Pinouts:  
–18-lead DIP  
Infinite EEPROM to RAM Recall  
CMOS and TTL Compatible I/O  
Power Up/Down Protection  
–16-lead SOIC  
10 Year Data Retention  
Commercial, Industrial and Automotive  
100,000 Program/Erase Cycles (E2PROM)  
Temperature Ranges  
DESCRIPTION  
TheCAT22C10NVRAMisa256-bitnonvolatilememory  
organized as 64 words x 4 bits. The high speed Static  
RAM array is bit for bit backed up by a nonvolatile  
EEPROM array which allows for easy transfer of data  
from RAM array to EEPROM (STORE) and from  
EEPROM to RAM (RECALL). STORE operations are  
completed in 10ms max. and RECALL operations typi-  
cally within 1.5µs. The CAT22C10 features unlimited  
RAM write operations either through external RAM  
writes or internal recalls from EEPROM. Internal false  
store protection circuitry prohibits STORE operations  
when VCC is less than 3.0V.  
The CAT22C10 is manufactured using Catalyst’s ad-  
vanced CMOS floating gate technology. It is designed  
to endure 100,000 program/erase cycles (EEPROM)  
and has a data retention of 10 years. The device is  
available in JEDEC approved 18-lead plastic DIP and  
16-lead SOIC packages.  
PIN FUNCTIONS  
PIN CONFIGURATION  
DIP Package (L)  
SOIC Package (W)  
Pin Name  
A0–A5  
I/O0–I/O3  
WE  
Function  
Address  
Data In/Out  
Write Enable  
Chip Select  
Recall  
A
A
A
A
1
2
3
4
5
6
1 6  
1 5  
1 4  
13  
12  
11  
10  
9
V
cc  
A
V
4
3
2
1
1 8  
NC  
cc  
1
2
3
4
5
6
7
8
A
4
5
1 7  
1 6  
1 5  
1 4  
13  
NC  
I/O  
I/O  
I/O  
I/O  
A
A
5
I/O  
4
3
2
1
3
A
2
3
CS  
A
A
I/O  
I/O  
I/O  
0
1
2
1
0
RECALL  
STORE  
VCC  
CS  
A
0
CS  
V
7
8
12  
WE  
RECALL  
ss  
STORE  
Store  
V
11  
WE  
ss  
+5V  
STORE  
9
10  
RECALL  
VSS  
Ground  
NC  
No Connect  
© Catalyst Semiconductor, Inc., Patent Pending  
Characteristics subject to change without notice  
Doc. No. MD-1082, Rev. P  
1

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