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CAT22C10JA-20TE13 PDF预览

CAT22C10JA-20TE13

更新时间: 2024-10-27 02:52:03
品牌 Logo 应用领域
CATALYST /
页数 文件大小 规格书
10页 74K
描述
256-Bit Nonvolatile CMOS Static RAM

CAT22C10JA-20TE13 技术参数

是否Rohs认证: 不符合生命周期:Transferred
零件包装代码:SOIC包装说明:SOP, SOP16,.4
针数:16Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.41
风险等级:5.13最长访问时间:200 ns
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
长度:10.3 mm内存密度:256 bit
内存集成电路类型:NON-VOLATILE SRAM内存宽度:4
湿度敏感等级:1功能数量:1
端子数量:16字数:64 words
字数代码:64工作模式:ASYNCHRONOUS
最高工作温度:105 °C最低工作温度:-40 °C
组织:64X4封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:PARALLEL峰值回流温度(摄氏度):240
电源:5 V认证状态:Not Qualified
座面最大高度:2.65 mm子类别:SRAMs
最大压摆率:0.04 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:7.5 mmBase Number Matches:1

CAT22C10JA-20TE13 数据手册

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CAT22C10  
256-Bit Nonvolatile CMOS Static RAM  
FEATURES  
Single 5V Supply  
Low CMOS Power Consumption:  
–Active: 40mA Max.  
Fast RAM Access Times:  
–Standby: 30 µA Max.  
–200ns  
–300ns  
JEDEC Standard Pinouts:  
–18-pin DIP  
Infinite E2PROM to RAM Recall  
CMOS and TTL Compatible I/O  
Power Up/Down Protection  
–16-pin SOIC  
10 Year Data Retention  
Commercial, Industrial and Automotive  
100,000 Program/Erase Cycles (E2PROM)  
Temperature Ranges  
DESCRIPTION  
TheCAT22C10NVRAMisa256-bitnonvolatilememory  
organized as 64 words x 4 bits. The high speed Static  
RAM array is bit for bit backed up by a nonvolatile  
E2PROM array which allows for easy transfer of data  
from RAM array to E2PROM (STORE) and from  
E2PROM to RAM (RECALL). STORE operations are  
completed in 10ms max. and RECALL operations typi-  
cally within 1.5µs. The CAT22C10 features unlimited  
RAM write operations either through external RAM  
writes or internal recalls from E2PROM. Internal false  
store protection circuitry prohibits STORE operations  
when VCC is less than 3.0V.  
The CAT22C10 is manufactured using Catalyst’s ad-  
vanced CMOS floating gate technology. It is designed  
to endure 100,000 program/erase cycles (E2PROM)  
and has a data retention of 10 years. The device is  
availableinJEDECapproved18-pinplasticDIPand16-  
pin SOIC packages.  
PIN FUNCTIONS  
PIN CONFIGURATION  
DIP Package (P)  
SOIC Package (J)  
Pin Name  
A0–A5  
I/O0–I/O3  
WE  
Function  
Address  
Data In/Out  
Write Enable  
Chip Select  
Recall  
A
A
A
A
1
2
3
4
5
6
1 6  
1 5  
1 4  
13  
12  
11  
10  
9
V
cc  
A
4
3
2
1
V
1 8  
1
NC  
cc  
5
A
4
2
3
4
5
6
7
8
1 7  
1 6  
1 5  
1 4  
13  
NC  
I/O  
I/O  
I/O  
I/O  
4
3
2
1
A
A
5
I/O  
3
A
2
CS  
3
A
0
A
I/O  
I/O  
I/O  
1
2
1
0
RECALL  
STORE  
VCC  
CS  
A
0
CS  
V
7
8
WE  
RECALL  
ss  
STORE  
12  
Store  
V
11  
WE  
ss  
+5V  
STORE  
9
10  
RECALL  
VSS  
Ground  
22C10 F01  
22C10 F02  
NC  
No Connect  
© 1998 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Doc. No. 25018-0A 2/98 N-1  
1

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